Ian’s I2S FIFO Re-clocker: Single-digit psec Jitter
Update (9/12/12): Adding RMS values is just simple addition; peak to peak values add by the root of sum of squares (Xilinx)
Update (9/3/12): updated adding RMS values (square root of the sum of the squares). This makes the RMS jitter numbers for the Musiland devices much better…
Update (8/31/12): updated jitter values after realizing that the FPGA jitter values are specified as peak-to-peak whereas the clock people use RMS values.
First of all, I am amazed at the level of professionalism form these group buys…
THE CURRENT STATE OF THE ART: 2-DIGIT JITTER
The venerable SPDIF receiver from Wolfson (WM8804) specifies its output jitter at 50 picoseconds RMS
FPGA-based designs with external clocks
Many in the current crop of state of the art USB-I2S interfaces are based on FPGAs. All FPGA or processor based approaches are limited by the added jitter to the clock whether it is derived inside the processor by a DCM (Digital Clock Manager) or whether the clock is taken from an external discrete oscillator. Once the clock enters the device, jitter will be added.
The amount of jitter added to the clock is typically specified in the data sheets. For example the Xilinx Spartan 3 FPGA specifies the added jitter to a clock signal as it is goes through the FPGA to be a minimum of one hundred picoseconds peak-to-peak. If there is integer division of the clock signal, then the jitter is 150 picoseconds peak-to-peak. If the clock is instead generated internally by the DCM, then jitter is higher, in the order of 250 picoseconds peak-to-peak (a DCM does multiplication and division on a reference clock signal in order to obtain the desired frequency, thus more operations resulting in more jitter).
There are ways to reduce this jitter somewhat by passing the derived clock to the built-in PLLs as described in the Clock Resource Guide [link], but in general, we are talking a minimum of 150 picoseconds peak-to-peak jitter values. (According to an engineer at Xilinx [link], peak to peak jitter converts to RMS jitter by 1ps RMS =~ 15 ps PP.)
In addition,one must also add the jitter from the source clock. For external, for discrete oscillators this jitter could be as small as < 1psed RMS to several psec RMS. A “typical” audio quality device would have ~ 2 psec RMS of jitter. If the clock comes from another device and not from a discrete oscillator, then one can assume that the jitter is much higher.
Thus the minimum jitter of an FPGA-based board is the added by the FPGA is ~ 10 psec RMS plus the jitter from the source clock. Not bad at all… (There is more jitter added from other factors such as the PCB layout, noise from the PS, etc)
Another current favorite are interfaces based on the XMOS single-core XS-1 device. I was not able to find jitter specification in the data sheet. However, an XMOS processor is likely the equivalent of an FPGA, because they compete in the same space, and one could assume that the jitter performance is similar to that of FPGAs. Thus we can also assume that the minimum output jitter is in the order of 10 ps RMS
FPGA-based designs with internally generated clocks
The Musiland devices derive the clocks from the FPGA clock managers (the DCMs). Two DCMs are used to generate the clocks. Each time the clock is processed by the DCM ~ 250 psec peak-t0-peak is added. Thus processing the clock by two DCMs will add SQRT(250**2+250**2)=24 psec RMS which is still pretty good.
The low end Musiland allows you to use one DCM to derive an approximate clock (good enough for audio) resulting in just 250 psec peal-to-peak of jitter or ~17 psec RMS of jitter.
In addition, there is the jitter from the source clock which comes from the USB chip, which could be in the order of 150 psec pp. In total, the jitter from a Musiland device using 2 DCMs to generate the clocks could be in the order of SQRT(24**2+10**2)~350 ps p-p, or ~24 ps RMS . This makes the Musiland devices quite a bit better than the well regarded WM8804/05 chips which are specified at 50 psec RMS
There is of course additional jitter caused by noise in the power, circuit layout, etc. So the above is a theoretical minimum. It is pretty obvious that the best devices are the ones using external clock sources rather than internally generated by the DCMs
Analyzing the current state of the art devices show that the dominant component of the jitter is the clocking device (the FPGA). The goal of Ian’s re-clocker is to lower the added jitter to single digit picoseconds RMS by attacking the dominant source of jitter.
The approach differs from current interfaces by first using a FIFO implemented in an FPGA to receive the data (same as everyone else), buffer the memory in memory (unlike everyone else) and then clock the data out with a clocking circuit that is separate from the FPGA. This way you separate the high jitter (or relatively higher jitter) domain from the low jitter domain.
The clock board is implemented with a simple flip-flop logic circuit and optionally with an additional clock fan-out device if more than one clock is supported. In addition, the clock board is powered by its own ultra-low noise regulators and further isolated from mechanical vibrations with rubber 0-rings.
Thus the jitter at the output is basically the jitter of clock plus the jitter of the flp-flop chip. According to some reports, the jitter added by a flip-flop is just “a few psec RMS”.
There are two versions of the clock board:
The single-clock board
- Single sample rate support (depends on the oscillator used. For example 44.1K SR requires a 11.2896MHz oscillator)
- MCLK is fixed at 256*FS
- 9 uV rms LDOs
The dual-clock board
- Automatic oscillator switching to support all sample rates 44.1Khz to 192Khz
- 9 uV rms LDOs plus enhanced high performace EMI filters
It is interesting to note that the D-type flip-flop in a prototype version of the Dual clock board, uses the PO74G74 which is a breakthrough device from a start-up called “Potato Semiconductor”. You can read the patented technology here: [link].
The shipping version of the Dual Clock board uses 74AUP1G79 (chip marking is “p79”) single flip-flops to re-clock the I2S signal. According to the designer, this device works equally well as the “potato chip”🙂. And in any case we are talking bandwidth capabilities >10x than the highest I2S clock rates on any of these devices
You can see these devices more clearly in this closeup of the matching SPDIF receiver that Ian developed (C9 and the regulator next to c15):
Since the added jitter by the circuitry is small, the final result may be determined to some extend by the quality of the crystal oscillator. The kit comes with “basic” oscillators to test its functionality. The end-user is to replace these oscillators with higher quality ones.