Modding Clocks in USB-I2S Board?
(Update 9/12/12): Updated adding RMS values to be straight addition). Peak to peak values add as root of sum of squares; RMS values add with simple addition (Xilinx)
(Update 9/3/12): Updated adding RMS values to be square root of sum of squares
We diy-types can leave any product alone. Soon after receiving the device we feel the urge to open the device and improve it 🙂
A reader asked about the wisdom of replacing the local oscillators with Crystek 957 types for the Amanero board. Keep in mind that two 957 clocks cost more than the board itself at the group-buy price.
Decided to some looking. This is what I found:
JITTER SPECIFICATION in DATASHEET
The output clocking device in the Amanero board is a Xilinx CPLD but the datasheet does not say anything about jitter in the clock circuitry. The closest cousin to that device is the Xilinx Spartan 3 FPGA which is used in many similar devices. The datasheet specifies a minimum jitter number of 150 psec peak-to-peak for clocks that are integer divided (as is the case to generate for example the bitclock or the LRclock). Keep in mind that this is added jitter by the FPGA.
From a Xilinx engineer [link]:
…Any clock, once it is inside the FPGA, will have roughly 100 ps peak to peak jitter imposed on it from all the internal switching that is going on, in the best case. If you have poor bypassing (decoupling), and poor signal integrity, that number can easily reach 1000 ps…
I am presuming that your 1ps source clock is 1 ps RMS, which is pretty darned great, which translates to 15 ps P-P (1ps RMS ~~ 15 ps P-P). As all jitter for Xilinx clocking is done in P-P jitter
Thus 1 ps RMS = 15 ps PP
And 150 ps PP ~ 10 psec RMS
(Note: after realizing that the FPGA people specify jitter as peak-to-peak values, I revised the FIFO reclocker post)
- We have the added jitter from the CPLD which is about 10 ps RMS (the oscillator outputs are connected to the CPLD and the master clock comes out of the DPLD)
- Then we have the jitter from the clocks which is about 2.4 ps RMS
- How about the jitter from the source? It seems to me that the jitter from the source will be nullified by the (asynchronous) re-clocking by the CPLD and does not propagate downstream. (If I am wrong, please post a comment)
Therefore, the theoretical minimum jitter value of the device is:
~ 12.4 ps RMS or 186 ps PP
(Actual calculation because we are adding RMS values we just use straight addition: total jitter=10+2.4 =12.4 )
and this is without counting any additional added jitter due to board layout, PS noise, etc. -Although the Amanero simplistic approach and the use of ADP-150 regulators would keep this to a minimum.
MODDING THE CLOCKS?
(Photo of the clocks are from Ian’s FIFO thread at diyaudio)
Is it worthwhile to replace the clocks with Crystek CCHD-957 clocks?
If we compare the jitter contribution between the CPLD and the on-board clocks, we find that the dominant component is that of the CPLD (plus any amount added by other factors such as PDB layout, PS noise, etc). The most you can eliminate is about 2 ps RMS out of a minimum of about 12.4 ps RMS or more. Not much of a change. But you’ll be the judge…