Sabre32

DATA SHEET: THE MISSING PARTS

[

A lot of information regarding the inner workings of the chip has been shared in the public forums, a lot of it coming from the lead designer of the DAC and much of it not even discussed in the data sheet. I summarized what I could find here: [link], and reproduced here for convenience

PIN DEFINITION

• Pin 8: Reset: 125: “Reset is not really required at all. You can do a chip reset if it somehow gets into a weird state (I am speculating) but I’ve never seen the need for it yet.”
• Pin 23- XO: 125: This pin can be left open when using an oscillator (rather than a crystal)
• Pin wiring to support Stereo and DSD-I2S-SPDIF: 145, 153
• Pin wiring to support I2S in hardware mode: 147: “If you just want I2S and nothing else, then just simply wire RSD0/RSD1/RSD2/RSD3 together and power-up.”

REGISTER DEFINITION

• Register 0-8, volume: 113
• Register 8, 18 Switching input format on the fly: 125
• Register 10 Jitter ON/OFF: 492
• Register 11 DPLL bandwidth: 575, 821
• Register 12, notch delay: 497, 758, 1315
• Register 14 DAC source: 153
• Register 14 true/pseudo diff (bit 3): 1683
• Register 14 IIR filter: 229, 2?
• Register 15 quantizer 35 and here
• Register 16 Automute: 159
• Register 17 Oversample bypass: 1279
• Register 37-45: Programmable filters: 1289

PROGRAMMING TIPS

• Switching inputs: 125: “Yes chip can change inputs on the fly (SPDIF to I2S, etc). I would mute the DACs then change the source, then un-mute for a nice smooth transition.”

DEVICE CHARACTERISTICS

• Output impdeance, each output pin: 114
• Change Input Format (SPDIF-I2S-DSD) on the fly: 125
• Choice of clock frequency: 127
• External oversampling: 241
• Jitter Eliminator corner frequency: 320
• Jitter performance (vs other DACs): 385
• DPLL bandwidth compared 9018 vs 9008: 1256
• DAC design priorities: 388
• Digital Volume Control: 456
• Filter passband ripple: 496
• Input levels and switching frequency: 574
• I2S bitclock requirement: 1578
• DAC SNR and THD Spec: 1532
• Built-in FIR filter characteristics: 241, 1295

DEVICE ARCHITECTURE

• Volume Control is done before Oversampling Filter: 113, 456 : “The volume control is done just before the oversampling filter on the digital data. It can be set to 0.5dB increments, but in order to avoid clicking when changing volume level, it actually goes through 64 intermediate levels to move 0.5dB. And op top of that, the volume does not instantly change when you request, but rather it changes logarithmically to the desired level. This results in a smooth transition.”
• Oversample Filter -> Noise Shaper -> Jitter Reduction: 258
• Inputs to DACs 3, 4, 7, 8 can be tied to inputs to DACs 1, 2, 5, 6 respectively: 153
• DAC internal data path (ES9008): 254
• DPLL uses (locks to) bit-clock: 1626
• Data reclocking: 319

INTELLECTUAL PROPERTY (PATENTS)

• Asynchronous sample rate correction by time domain interpolation
• System and method for digital volume control
• Device and method for signal processing
• Asynchronous Sample Rate Converter
• Low Noise Digital to Analog Converter with Audio Applications
• Low noise digital to signal interval converter with audio applications

PRESENTATIONS

• High End Audio DACs

OTHER

• Buffalo DAC I Schematic: 189
• White Paper: ESSTech
• Experimental Results on best DPLL settings: 1853

DATA SHEET

You can get a copy of the datasheet through the distributor in your country. Unlike other chip vendors, it is not available for download (don’t know why).

REGISTER DEFINITION

[b]

Register 12

Notch Delay. There is very little information on this register. This post [785] Indicates that with 6-bit quantizer “the n/64 notch delay should give the best performance”

|0|x|x|x|x|x|x|x| Dither Control: Apply
|1|x|x|x|x|x|x|x| Dither Control: Use fixed rotation pattern
|x|0|x|x|x|x|x|x| Rotator Input: NS-mod input
|x|1|x|x|x|x|x|x| Rotator Input: External input
|x|x|0|x|x|x|x|x| Remapping: No remap
|x|x|1|x|x|x|x|x| Remapping: Remap DIG outputs for “max phase separation in analog cell”

|x|x|x|0|0|0|0|0| No Notch
|x|x|x|0|0|0|0|1| Notch at MCLK/4
|x|x|x|0|0|0|1|1| Notch at MCLK/8
|x|x|x|0|0|1|1|1| Notch at MCLK/16
|x|x|x|0|1|1|1|1| Notch at MCLK/32
|x|x|x|1|1|1|1|1| Notch at MCLK/64

|0|0|1|0|0|0|0|0| Power-on Default

Register 13

DACx Polarity [link]

• Defines the polarity of DACx relative to its input. This may sound obvious but it is not so obvious if the input of a DAC is internally remapped to take its input from another DAC. When the input is remapped, the phase applied propagates to the other (remapped) DAC. This has the following implications:

– When using “in-phase” then there is nothing to worry, all dacs whether with inputs remapped or not will all be in-phase
– When using “anti-phase”, then the phase is also propagated to the remapped DAC so that the phase setting in the remapped DAC is also applied to the propagated phase

Example: In register 14: remap the source of DAC3 to be DAC1. In register 13: set polarity of DAC1 and DAC3 to be “anti-phase. The output of DAC1 will be “anti-phase”; the output of DAC3 will be “in-phase”: the anti-phase from DAC1 has been propagated to DAC3 and DAC 3 applied “anti-phase” to “anti-phase” resulting in “in-phase”

Register 14

|0|x|x|x|x|x|x|x| Source of DAC8 is DAC8 (D)
|1|x|x|x|x|x|x|x| Source of DAC8 is DAC6 (Use this to match BII input wiring)
|x|0|x|x|x|x|x|x| Source of DAC7 is DAC7 (D)
|x|1|x|x|x|x|x|x| Source of DAC7 is DAC5 (Use this to match BII input wiring)
|x|x|0|x|x|x|x|x| Source of DAC4 is DAC4 (D)
|x|x|1|x|x|x|x|x| Source of DAC4 is DAC2 (Use this to match BII input wiring)
|x|x|x|0|x|x|x|x| Source of DAC3 is DAC3 (D)
|x|x|x|1|x|x|x|x| Source of DAC3 is DAC1 (Use this to match BII input wiring)
|x|x|x|x|0|x|x|x| Pseudo Differential
|x|x|x|x|1|x|x|x| True Differential (D)
|x|x|x|x|x|0|0|x| IIR Bandwidth: Normal (47K for PCM)
|x|x|x|x|x|0|1|x| IIR Bandwidth: 50K (for DSD) (D)
|x|x|x|x|x|1|0|x| IIR Bandwidth: 60K (for DSD)
|x|x|x|x|x|1|1|x| IIR Bandwidth: 70K (for DSD)
|x|x|x|x|x|x|x|0| FIR Rolloff: Slow
|x|x|x|x|x|x|x|1| FIR Rolloff: Fast (D)

Effect of IIR Bandwith on signal (I got these traces from here: [link]). These traces show the effect of the IIR bandwidth setting on an incoming 30KHz signal. Notice the roll-off of the peaks when the bandwidth is decreased. [I don’t know what is the audible effect, except that it filters out of band artifacts]

From left to right: IIR=50K, IIR=60K, IIR=70K

Frequency response of the two built-in filters (from Stereophile)

Step response of FIR Rolloff setting: Fast vs Slow (traces are from here: [link])

In comparison, the filters of the AK4399 DAC show the following response: Fast roll off and Minimum phase

The ESS 9018 does not have a minimum phase filter. Minimum phase filters have been incorporated into modern DACs because they do not exhibit pre-ringing. The FIR filters in the ESS DAC are “standard” linear phase filters.

Register 15

Quantizer setting [35] [742] [1695] [2396]

The quantizer value affects one pair of DACs (independently) as follows:

• 00= 6-bit
• 01= 7-bit
• 10= 8-bit
• 11= 9-bit

The 4 pair of DACs are controlled by the 8-bit register:

• |xx|xx|xx|xx| (the 8-bit register)
• |DACs 6, 8|DACs 2, 4|DACs 5, 7|DACs 1, 3|

Example register values:

• |0|0|0|0|0|0|0|0| : All DACs in 6 bit, “best all-around performance” 8-channel input routed to 8-channel output
• |0|1|0|1|0|1|0|1| : All DACs in 7 bit, reduction of out-of-band noise. Also 8-channel input routed to 8-channel output
• |1|0|1|0|1|0|1|0| : All DACs in 8bit, further reduction of out-of-band noise. Inputs 3, 7, 4 and 8 are NOT needed (Input 3 is merged with 1; 2 with 4; 5 with 7 and 6 with 8). This result in 4 inputs routed into 8 outputs
• |1|1|1|1|1|1|1|1|: All DACs in 9bit, further reduction of out-of-band noise. Only inputs 1 and 2 are needed. 2 channels input routed to 8-channels at the output
• |1|1|1|1|0|0|0|0|:  Channels 2, 4, 6, and 8 have been combined into a single channel. We have a 5-channel DAC: The even side is one channel; the odd side is 4 channels.

Register 16Automute Loopback

• Default is off (does not mutes when detecting no music. Probably a good idea to leave it off to prevent the volume ramp up after mute to cut into the next track as reported here: [link]

Register 17

|1| | | | | | | | Mono Right (if set for MONO)
|0| | | | | | | | Mono Left (if set for MONO) (D)
| |1| | | | | | | OSF (Oversample filter) Bypass
| |0| | | | | | | Use OSF (D)
| | |1| | | | | | Relock Jitter Reduction
| | |0| | | | | | Normal Operation Jitter Reduction (D)
| | | |1| | | | | SPDIF: Auto deemph ON (D)
| | | |0| | | | | SPDIF: Auto deemph OFF
| | | | |1| | | | SPDIF Auto (Only if no I2S on pins) (D)
| | | | |0| | | | SPDIF Manual (Manually select SPDIF input format)
| | | | | |1| | | FIR: 28 coefficients (D)
| | | | | |0| | | FIR: 27 coefficients
| | | | | | |1| | FIR: Phase invert
| | | | | | |0| | FIR: Phase NO invert (D)
| | | | | | | |1| All MONO (Then select Mono L or R)
| | | | | | | |0| Eight channel (D)

OSF bypass [link]:  Bypasses the internal oversampling FIR filter and expects the data to be at 8X oversampling according to the datasheet.  The data is sourced directly to the IIR filter. (The DAC expects the incoming data at 8x FS because internally it applies an 8X oversampling when the oversampling is enabled). The next stage is the asynchronous sample rate conversion (the jitter eliminator) where the data is re-sampled to a higher rate still [link].  The “final” sample rate -the rate coming out of the ASRC is entirely determined by the master clock, and it is fixed at MClk/64 [574]. Thus for the 100MHz Buffalo, the resampled rate is 1.5625 MHz and for the 80 MHz Buffalo, the resampled rate is 1.25 MHz [link]

You can read my results on oversampling bypass here: [link]

SPDIF Auto [link]:  The chip will autodetect if the input stream on data1 is SPDIF or not. If its not, it will try to see if it is I2S or DSD. This is the default power-on setting for the Sabre32 chip. If the spdif input is wired to data1, then detection of input format is automatic. Buffalo II takes advantage of this feature for automatic detection of input format. Notice that it requires that spdif be wired to “data1” input pin.

NOTE on auto/manual SPDIF selection
Apparentely (while programming the chip), auto detection of spdif and I2S (with I2S/DSD enabled in reg 8), only works when the DAC powers up. Once you turn off auto-SPDIF and then turn on auto-SPDIF, it will not work with SPDIF input format while reg 8 is still set for I2S/DSD. In order for SDPIF to work, reg 8 must be set for SPDIF and reg 17 for auto-SDPIF.

In summary:

Reg 17: Auto Spdif	Reg 8: Source	Result
ON	I2S/DSD	SPDIF  is ON: Only works when DAC starts with these (default) settings
ON	SPDIF	SPDIF ON: Works even when auto-SPDIF is set to OFF, then to ON. For manual selection of SPDIF, use this setting
OFF	SDPIF	SPDIF OFF, I2S OFF. I am not sure what is this setting for
OFF	I2S/DSD	I2S ON. Use this to manually select I2S input

Writing to register 18 (selecting the spdif input line) alone will not work if auto-SPDIF is off. You need to turn on auto-SPDIF and if using SPDIF input line other than #1, you need to select the input line with register 18. This behavior has been fully tested [link]

Register 18: Spdif Source

|0|0|0|0|0|0|0|1| SDPIF Input: Data1 pin (D) (In BII, spdif connects to this pin)
|0|0|0|0|0|0|1|0| SDPIF Input: Data2 pin
|0|0|0|0|0|1|0|0| SDPIF Input: Data3 pin
|0|0|0|0|1|0|0|0| SDPIF Input: Data4 pin
|0|0|0|1|0|0|0|0| SDPIF Input: Data5 pin (In BuII, spdif also connects to this pin)
|0|0|1|0|0|0|0|0| SDPIF Input: Data6 pin
|0|1|0|0|0|0|0|0| SDPIF Input: Data7 pin
|1|0|0|0|0|0|0|0| SDPIF Input: Data8 pin

Auto spdif only works if the source is connected to Data 1. If the source data is connected to the other inputs, it requires manual selection.

Register 19

DACBx Polarity [link]. Register 19 is used in conjunction with register 13

• Defines the polarity of DACBx in relation to DACx (thus it does not define absolute polarity). In normal operation, all DACBx should be in anti-phase relation with DACx Thus:

– If DACBx is set to “anti-phase”: flipping the polarity of DACx will automatically also flip the phase of DACBx
– If DACBX is set to “in-phase”: DACBx will always follow the polarity of DACx

SOME PRACTICAL USES FOR REGISTER SETTINGS

[b]

LEVERAGING INTERNAL SOURCE SELECTION

Manual vs automatic: the Sabre DAC has two modes of internal input switching: manual and automatic. In automatic mode, the chip switches to the appropriate input format (I2S, SPDIF or DSD) depending on the signals present in the input pins. In manual mode, you tell the chip what kind of input format to lock to and which pins to use as input.

Buffalo II DAC was designed for ease of use by cleverly combining 4 inputs and automatically supporting and detecting SPDIF, I2S and DSD in stereo mode. The default mode of operation in BII is automatic input format selection. However, there are cases where manual selection is preferred especially when dealing with multiple inputs. For example the chip  has an internal MUX for 8 spdif signals and can also internally re-rout and duplicate signals.

I did an experiment having both a SPDIF and an I2S signals wired (and live) to the BII DAC and using one SPDT switch (h/w switch) and firmware (s/w switch) to switch between the two inputs. It works as I expected. Both I2S and SPDIF signals are live at all times. However you must follow a switching sequence in order to avoid noise:

	From	To	H/W switch first	S/W switch first
1	I2S	SDPIF	Noise. Incorrect sequence	No Noise. Correct sequence
	I2S	SDPIF	DAC is set for I2S and you switched one of the lines to SPDIF. The DAC is still locked to the bitclock line but now it is receiving SPDIF data instead	DAC switches to SPDIF. It cannot lock to I2S data because it is expecting SDPIF data. In the meantime the DAC is muted
2	SDPIF	I2S	No Noise. Correct sequence	Noise. Incorrect sequence
	SDPIF	I2S	DAC is set for SPDIF and you switched to an I2S signal. This will cause the DAC to loose lock and be muted	DAC thinks all data lines are I2S when they are not (one is still spdif until you do the h/w switch). The DAC can still lock to the bitclock line but the LRCK or DATA line is having spdif data which is interpreted as noise

If you are using a manual switch (one pole switch), even thought the solution works, it is not optimal as one cannot follow this sequencing every time. However, if one does everything in s/w (that is, using an Arduino and  relay), then one can automate this sequence. Of course if you are using a 4 pole switch where you can completely switch out the I2S signal, then keep the internal switch in automatic and yo get the same functionality.

This is probably the most you can do in terms of combined h/w-s/w switching in BII. The way the input pins are hardwired prevents further flexibility. For example, only one SPDIF input can be used in BII.

Bufflao III

With  BIII, all input pins are available and not pre-wired like BII. Therefore you can take full advantage of manual (internal) switching.  You could use a combination of h/w (relays) and s/w (firmware) to accomplish different source switching configuration. You could for example:

• Permanently wire 1 8-channel I2S and 3 SPDIF channels to the BIII DAC and do the input switching is software.

• Switch up to 8 channels of SPDIF without external components

• Use the quantizer bit  size to switch from 8 channel input to 4-channel or 2-channel input and replicate the signal to all the internal DACs without external h/w switching of the inputs (quantizer section explains how this is accomplished)

QUANTIZER SETTING

A lot of the Sabre DAC quantizer (and related) discussions were made 2-3 years ago when the company first released the 24-bit version ES9008. Since then, ESSTech released the 32 version of the DAC and “recommended” the use of chip default settings. However, the different settings remain available and accessible to diy tweakers like ourselves :-).

The core benefit of changing the quantizer size is that of reduced HF noise as explained here:

6-bit vs 9-bit quantizer: 785

• The HF noise coming out of the DAC in 6bit mode is noticeably more than it is in 9 bit mode. DAC output seems to require less filtering. Running the analog section with a less aggressive filter has some nice benefits (better slew rate etc) to the final audio.

• In 6 bit mode to get the best performance you should use the n/64 notch delay.

In addition, I tested all possible combinations of quantizer settings and determined the valid settings: [link].

Sound impressions on quantizer setting [link]

Reported is a comparison between 9-bit pseudo differential vs 8-bit true differential setting:

Sonice difference, 9-bit vs 8-bit true differential (only register settings were changed)

Under 9-bit quantizer mode, the sound is less bold, and attacks are more solid, noises contained in recordings are more audible. Although those difference are very small amount and It required me repetitive comparison over and over.

Merging channels

A byproduct of the noise reduction setting is a reduction of available channels.

As you increase the quantizer bit size, the DAC internally turns off the digital sections for half of the DACs and replicates the output to all the analog sections of the DACs. Further increase of the quantizer bit size further turns off the digital sections for half of the remainder DACs resulting in using only one quarter of the digital sections of the internal DACs. Thus, whereas all the analog sections are always fully utilized, the number of channels available in the DAC depends on the quantizer setting as follows:

	Quantizer	Input Channels	Output
1	6-bit	8 (All)	8×1
2	7-bit	8 (All)	8×1
3	8-bi	4 (#1,#2,#5,#6)	4×2
4	9-bit	2 (#1 and #2)	2×4

According to Dustin Forman in this post: [redacted here for clarity]

One way to add DACs together is to simply duplicate the input to many DACs and sum them up at the output. This buys 3dB DNR improvement every time you double the amount of DACs. Basically uncorrelated noise adds RSS and signals add normally. Another way would be to use a larger bit QUANTIZER and route the signals from the QUANTIZER to 2 DACs, but the noise shaper now has an extra bit in it.

This chip does both. You can 1- simple duplicate the data input header and then add up the outputs in an analog circuit on the board, or 2- you can program the chip to use a larger QUANTIZER. Doing this prevents the need to send the same data to all the inputs since now a certain DAC Channel is routed into 2 DAC outputs (one channel into two channels).

The DAC is normally a 6-bit QUANTIZER, with the DACx being the summation of the 6 bits, and DACxB being the summation of the inverse of the SAME 6 bits. This is the best all round performance mode, and this is why the datasheet says register 15 needs to be set to 8′b00000000.

Setting this register to 8′b01010101, which by the way was the mode I thought would work best base on my prototype design, (and that is why it is the default configuration) the DAC becomes a 7-bit QUANTIZER reducing out of band noise. I simple divide up the 7-bit number coming from the QUANTIZER into 2 6-bit numbers and invert 1 of them. Then I send off these new 2 6-bit numbers which the difference is mathematically identical to the original 7-bit number from the QUANTIZER and ship them off to the analog section. This also results in 8 channels at the input being routed to 8 channels at the output. (A 7 bit number can have 128 levels, a 6 bit number can have 64 levels. Two 64-bit number can represent 128 levels if added together)

Now, let’s go further (we are only 1/2 down this road). if you set the register 15 to be 8′b10101010 then you get a DAC with an 8-bit QUANTIZER, out of band noise decreases more and so on. Now I shut off 1/2 the internal logic since it is not required, only inputs 1,2,5,6 are now needed since an 8-bit output can be spliced into four 6-bits numbers. Channel 1 is merged with channel 3, 2 is merged with 4, 5 is merged with 7, 6 is merged with 8. This arrangement is to keep the merged channels analog sections as close as possible for device matching inside the chip.

This gobbles up 2 analog sections [You still have 2 analog sections per DAC-channel active, but ½ of them take the input from another DAC-channel as indicated above] per input now. This is why 1/2 the digital section is shut off. So this can make you a 4 channel DAC while putting data into only the first 4 channels. [4 Channel -> 4 DAC-Channels -> 8 DACs (8-bit quantizer) -> 16 analog sections]

Ok, let’s go further, how about a 9-bit QUANTIZER? sure why not. Setting register 15 to 8′b11111111, I shut off 6 of the channels internally and only channels 1 and 2 inputs are routed to the analog sections. Well it is probably obvious by now why, but here it is again: 1 9-bit number can be broken into 8 6-bit numbers. Now route the 8 6-bit numbers to the analog sections (remember that each section is DAC and DACB so there are 2 analog sections per DAC or 16 total in the chip) so now with each input taking 8 analog sections, we have 2 channels.

Mr Bunpei and Mr RayCtech have this to say regarding the quantizer [2229]

The basic hardware design of one Analog DAC section of ES9018 is of 6 bit. A “quantizer bit length expansion” technique is a combination of multiple 6 bit DAC sections to obtain higher resolutions equivalent to those of 7, 8 or 9 bit DAC.

Let’s think of a definite case.
A six bit DAC should have 64 levels including 0.
6 bit: values … 63 – 0

A nine bit DAC should have 512 levels including 0.
9 bit: values … 511 – 0
In the case we need to yield 9 bit levels by a combination of eight 6 bit values:
Target value 511
DAC1 – 63
DAC2 – 63
DAC3 – 63
DAC4 – 63
DAC5 – 63
DAC6 – 63
DAC7 – 63
DAC8 – 63
————————
Total 504

Alas, the sum of 8 individual DAC output is less than the ideal target value 511! How can we compensate the shortage?

0 is a value so you get the 512.
In 9 bit true mode it is actually 1024 levels as each phase have 512…
If you read what Dustin have written previously in this thread you will find that there are not any 6 bit DAC engines at all…
It is only a default of 6 bit data that are sent to the DAC section…

DPLL SETTING

The Sabre DAC uses the Phase Lock Loop to lock unto an incoming signal. For I2S,  it locks to the bitclock.

DPLL Values: The DPLL bandwidth can be set to the following values: “lowest”, “low”, “medium-low”, “medium”, “medium-high”, “high”, “highest” and “best”; there is also a 128x setting which apparently multiplies the bandwidth values x128.

The DPLL has adjustable bandwidth. Setting the bandwidth to its lowest value results in maximum jitter reduction. However if the bandwidth is “too low”, the DPLL will loose lock and you will hear dropouts. Thus the usable lowest bandwidth setting is one where no dropouts occur. I have done extensive testing with the different settings of the DPLL. Here is a summary on how it behaves:

• “Best” setting works all the time for everything

• “Lowest” works for SPDIF input but never works for I2S input except for a few exceptionally modded I2S devices. Thus the lowest setting depends on the input format

• The lowest setting depends on the incoming sample rate. The higher the sample rate, the higher the lowest setting

• The lowest setting will not work when the DAC is cold (right after power-0n). The “warm up” period is 15-30 minutes

I wrote 3 posts on the DPLL describing its behavior further:

• Post 1: [link]
• Post 2: [link]
• Post 3: [link]

Relation of dpll bandwidth setting in SPDIF and I2S

Fidelix indicate that the DPLL bandwidth setting for I2S is 64x smaller than in SPDIF. This was confirmed by the manufacturer. So:

• “Lowest” is 64X smaller in I2S than “Lowest” in SPDIF (1/64 the same setting in SPDIF)
• “Low” is 32X smaller in I2S than “Lowest” in SPDIF
• “Mid-Low” is 16X smaller in I2S than “Lowest” in SPDIF
• “Mid” is 8X smaller in I2S than “Lowest” in SPDIF
• “Mid-High” is 4X smaller in I2S than “Lowest” in SPDIF
• “High” is 2X smaller in I2S than “Lowest” in SPDIF
• “Highest” is the same as “Lowest” in SPDIF

TECHNICAL DETAILS

[b]

Oversampling frequency of the ASRC

The asynchronous sample rate conversion (the jitter eliminator) the data is re-sampled to a higher rate [link].  The “final” sample rate -the rate coming out of the ASRC, is entirely determined by the master clock and it is fixed at MClk/64 [574].

• For the 100MHz Buffalo, the resampled rate is 1.5625 MHz
• For the 80 MHz Buffalo, the resampled rate is 1.25 MHz [link]

More on oversampling here: [link]

Digital Volume: [Post 133]

The volume control is done just before the oversampling filter on the digital data. It can be set to 0.5dB increments and in order to avoid clicking upon volume level changes, it  goes through 64 intermediate levels to move 0.5dB. In addition, the volume does not instantly change when you request, rather it logarithmically moves to the desired level. The way this shows up in a system implementation is that the sound softly changes levels.

DAC Resolution discussion: [link]

A recent Audio Asylum discussion on true 32-bit resolution involved the Sabre DAC and, amongst others, Thorsten Loesch of Abbingdon Music Research and finally the Sabre’s own designer Dustin. I’ve reproduced it here for posterity in the context of our review

Input Pin Mapping:

Pin	SPDIF	I2S	DSD	BII
DATA_CLK	–	Bit Clock	Bit Clock	DCK
DATA1	SPDIF 1	LRCK	Data 1	D1
DATA2	SPDIF 2	Ch1/Ch2	Data 2	D2
DATA3	SPDIF 3	Ch3/Ch4	Data 3	Gnd
DATA4	SPDIF 4	Ch5/Ch6	Data 4	D2
DATA5	SPDIF 5	Ch7/Ch8	Data 5	D1
DATA6	SPDIF 6		Data 6	D2
DATA7	SPDIF 7		Data 7	Gnd
DATA8	SPDIF 8		Data 8	Gnd

BII Input wiring (graphically)

(A newer version of the diagram is in the BII page)

AVCC Power Consumption [link] versus AVCC voltage. The DAC operates from 1.8V to 4.0V. This also means that the output voltage offset of the DAC (=AVCC/2) will also vary with the AVCC voltage.

ASRC bypass [link]

You can use the ASRC if you like – or not by simply clocking the XIN pin synchronously (at an integer multiple) to the BCLK. Then the ASRC drops itself out, reverting in this case to a more conventional method as the other DACs I’m aware of do.

More on ESS’s SRC technology [1985]

ESS’s claims regarding the SRC pertain to the actual interpolation process. They have done an absolutely splendid job there. The thing that causes problems is the ratio estimator (the bit that works out exactly what sampling time to interpolate). The bandwidth is too high which lets through time quantization errors. The circuit samples the incoming clock signal using its reference clock. This results in the addition of jitter with a peak-to-peak value of one reference clock period (e.g. 25ns for a 40MHz reference clock). Next the number of ref clock periods in one input clock cycle are counted and this constantly changing number is fed into a low-pass filter which outputs a cleaned-up version of the ratio between the reference and input clocks. This ratio is then used to space the “virtual resampling points” calculated by the interpolator. Of course the low pass filter doesn’t output pure DC. The spectrum of the counter output consists of mix products between the two clocks. The filter can only attenuate those. The attenuated spectrum shows up as close-in FM sidebands exactly like jitter. DNR and THD measurements ignore those. The SRC successfully removes high-frequency jitter, thus guaranteeing good SNR, but it adds low-frequency phase modulation of the signal that wasn’t even present in the input clock. All SRC’s do this but the bandwidth of the low-pass filter determines whether this is an issue or not.

Oversampling filters: link

The antialiasing filters built into ESS’s parts are linear phase. The default fast rolloff filter is much the same as the linear phase “brickwalls” found on other DACs. ESS’s slow rolloff has a noticeably wider transition band than the slow roll linear phase filters chosen by other manufacturers and hence is a good choice if one is attempting to minimize the amount of preringing the antialiasing filter creates in the output signal. However, after doing a variety of ABX trials with similar filters I found the filter’s impulse response was audible with just about 100% discrimination. Intermediate phase filters with reduced preringing scored better, though not as well as minimum phase filters. Since ESS’s built in filters are all linear phase this means the only compete option ESS has against Cirrus and Wolfson in this regard is for one to synthesize one’s own minimum phase-ish filter and program it into an ES901x series DAC. This is somewhat interesting for the control it offers but, in practice, it means you can maybe pick slightly different tradeoffs than Cirrus and Wolfson did and then do quite a bit of optimization work to make your filter as good as the turnkey options available in other parts.

TECHNICAL PRESENTATIONS

Two presentations by Martin Mallison, CTO, ESS Technology

• Noise Shaping Sigma Delta Based DaACS [link]
• Digital Jitter and Volume Controls, Martin Mallison, CTO, ESS Technology [link]
• The presentation slides are here: [link]