Home > DIY HiFi, TEST > Buffalo II I2S Interface (Again)

Buffalo II I2S Interface (Again)

NOTE: Although this post reads like there is a problem with the DAC, what I am doing here is reporting a particular behavior of the DAC with certain (the most picky, I would say) settings are made in the registers. Choosing the right settings will allow the DAC to perform flawlessly (as you can see in the comments). Also I am particularly NOT saying that the Buffalo II implementation of the Sabre DAC is causing this behavior but that is the DAC I am currently using.

I spent quite a bit of time investigating the locking issue with the I2S interface of the Buffalo II (v1.0) DAC. Keep in mind that we want to use I2S because “conventional wisdom” says that I2S is better than SPDIF and in particular “it has less jitter”. Keep also in mind that the SPDIF interface in Buffalo works flawlessly with the DPLL setting at “Lowest” and that increasing the DPLL bandwidth will allow more jitter to pass through.

The “problem” is that the DAC (when using the I2S interface) will loose signal-lock which results  in dropouts lasting a fraction of a second each. The severity of the problem depends on the DPLL bandwidth setting and the time since power-on of the DAC.

In my system, feeding the DAC with a Musiland Monitor USB interface, I was able to eliminate most of the dropouts by setting the DPLL bandwidth to “Medium-Low”. This setting is UP two notches from “Lowest” setting, which is the lowest bandwidth of a total of 7 possible settings (there is an 8th setting with zero bandwidth that prevents locking into the signal)

Additionally, when the DAC is first powered on, the dropouts are much worse, and even setting the DPLL bandwidth to “Highest” would NOT solve the problem. However, as the DAC “warms up”, the number of dropouts becomes smaller until reaching a steady state.

In my system, steady state is reached about ~15 minutes after power-on. At this time, setting the DPLL bandwidth to “Lowest” or “Low” would result in several dropouts within each song. Setting the DPLL bandwidth to “Medium-Low” would result in a dropout every few/many songs.

I did not test whether higher bandwidth would completely eliminate the dropouts but one report (see my previous post) indicate that even at this setting, the problem is not completely eliminated. However, setting the DPLL bandwidth to “Highest” may completely obliterate the advantages of using the I2S interface since the SPDIF interface works perfectly with the DPLL bandwidth set to “Lowest”

I can report that  I2S  at “medium-low” DPLL BW sounds no worse than SPDIF at “lowest” DPLL BW. In fact is seems to sound better, the music with “more sparkle”.  One reader of this blog has indicated that the I2S interface sounds better for him (see previous post).

In any case, at least there is a quest to achieve “lowest” DPLL setting with I2S interface which is something that makes this hobby fun. I can see this happening through:

  • More tweaking of the registers in the Sabre32 DAC
  • More tweaking of the Musiland Board to lower the input jitter
  • ESSTech tweaking the chip to figure out/fix why SPDIF can lock with “lowest” setting and I2S cannot

Also, I have improved the code to support I2S and enable more settings. I will publish that shortly after I clean it up. See my previous post on this subject to understand this issue some more.

Update 1/4/11: This material was posted previously but updated here with the latest information

Reports of having problems with I2S/DSD interface into Sabre32 DAC (the Sabre32 DAC implemented in different products, not just the Buffalo II DAC. So the “problem” is associated with the DAC chip)

To reiterate, the “problem” means using I2S and setting the DPLL bandwidth to “lowest”

  1. Hiface Evo [Link]
  2. TPA USB board based on the PCM2707 chip feeding Buffalo II DAC [Link]
  3. Musiland MINI, based on Spartan FPGA feeding Buffalo II DAC [This post]
  4. Teralink-X2 based on TENOR TE7022L and 1ppm TCXO feeding Buffalo II DAC [Link]
  5. AudioGD ESS-based DAC NFB-7 fed from Audio GD sources [Link]. Audio GD has discontinued the product right after launch
  6. “Manufacturer X” converting I2S into SPDIF before feeding the DAC [Link]
  7. SDTrans192 [Link] feeding modified Buffalo II DAC with better clocks and other mods. A good summary here [link]
  8. ElectrArt USB Interface and SACD players feeding Buffalo II DAC and Fidelix CAPRICE DAC : best DPLL bandwidth is medium-low [Link]
  9. SDTrans192 feeding a diy, highly customized implementation of Sabre32 DAC. This was previously reported as having no lock problem with lowest DPLL setting [Link]
  10. NeoY2K DAC [Link]
  11. XMOS USB 2.0 reference board (Link)
  12. exaU2I (Link). This basically proves that with the default setting at power on, the DPLL is using “best” and thus, no hiccups.

Reports of NOT having problems with I2S interface into Sabre DAC

  1. Highly modified Hiface USB interface feeding  Dual Mono Buffalo DAC II  [Comment section in this post]
  2. SDTrans192 [Link] See #9 above
  1. Bunpei
    January 3, 2011 at 00:34

    It’s a well-summarized article! I completely agree with these contents.
    According to my experience, the “warm up” effect can be interpreted as a better “frequency stability” of not the DAC chip but the master clock oscillator on the DAC.

  2. RayCtech
    January 4, 2011 at 20:32

    I investigated this “problem” and found two possible solutions….
    As it happens we all have introduced this “problem” by using other than the ESS recommend default DPLL settings😉
    One of the solutions to cure the “DPLL” was to use the ESS recommended “default” settings for the DPLL LOL!!!!
    I have now verified that this have been the cause my Sabre32 have worked perfectly all the time..
    I had not bothered to “tweak” the DPLL settings due to when I tested this a year or more ago I found no improvements…

  3. Russ White
    January 6, 2011 at 04:18

    Generally people only complain when something does not work with what ever source they have.

    Honestly, I am not saying I can answer what might be going on in every case, but I can tell you there are thousands of Buffalo DACs out there in the hands of users, and a very large number using I2S. It hardly surprises my to see several having lock issues.🙂

    As for the PCM2707 I2S output, I have never really loved it. It’s only ok, but has a lot of jitter, so you really need to open up the DPLL for that source.

    What I understand from Dustin is that the ES9018 introduced a much narrower DPLL bandwidth setting than the ES9008 had. There is a register you can set to get it to act the same. It basically multiplies the DPLL BW by 128. My suggestion is if your I2S source is having issues change that register. The register is 25[0].

    The DPLL is so good it will still reject a lot of the jitter, it will certainly be no worse than the WM8741.🙂

    I hope that helps you out.

  4. Hifiduino
    January 6, 2011 at 05:42

    Hi Russ, thanks for your comments. You are right, people with no problems would not be complaining about it. There may be hundreds of implementations that are working fine that we don’t hear about it.

    But this is not really a complain as much as reporting observed behavior. As I said, I2S with higher DPLL bandwidth seems to sound better than SPDIF with lowest DPLL bandwidth. Maybe ESSTech is watching these conversations and may improve upon their already excellent DAC, which is a good thing. And I have not discounted my USB inteface being the source of the problem. When I get a chance I will work on the clock and power supplies.

    Further, this is diy audio, which sort of translate to “obsesive pursuit of perfection”🙂. And if it werent for the superb and affordable kits you have developed for us, we wouldn’t be writing about it🙂. To be honest, I am more than happy with what you and Brian have done for us in the diy community. I Don’t expect any thing more.

    Your suggestion for register 25 (which is the same as what RayCTech has suggested) will be in the next version of the s/w. When selecting SPDIF it will default with “Lowest” DPLL BW setting. When selecting I2S it will default with “Best” DPLL BW setting, as indicated in the datasheet.

  5. Russ White
    January 6, 2011 at 11:57

    Not exactly the same there are two registers there. One, basically lets the chip dictate the DPLL on its own or lets you decide. The other multiplies your chosen setting by 128.

  6. Bunpei
    January 8, 2011 at 01:22

    I’d like to know whether the output of “The Metronome ASRC Module” have no “unstable lock on the lowest DPLL BW” issue or not. If the module is effective for solving the situation, I’m eager to purchase the product.

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  1. May 9, 2011 at 01:18
  2. August 16, 2011 at 17:29
  3. March 12, 2012 at 16:34

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