Sabre32 DAC I2S: Further Experiments
As you may know, the implementation of the Sabre32 DAC I am using is the Buffalo II DAC. However, I believe these observations apply to the Sabre32 DAC chip in general as there are other reports indicating similar behavior but with different implementation.
OPUS/WM8804 SPDIF RECEIVER
I rebuilt my trusty OPUS receiver board and LCDPS supply. The OPUS receiver board is based on the Wolfson WM 8804 SPDIF transceiver chip. It boasts 50 ps period intrinsic jitter (In the photo, it is the module in the middle on the white wood stripe). In fact some implementations use the WM 8804 as a signal conditioner (and jitter reducer) for spdif signals.
I connected the spdif output of the Musiland 01 MINI to the receiver board and the I2S output of the receiver board to Buffalo II. I wanted to test the different DPLL bandwidth settings on this source. Specifically I wanted to know if Buffalo could lock onto an incoming I2S signal with the DPLL bandwidth set to “lowest”.
The behavior of the DPLL setting with the OPUS/WM8804 receiver board is exactly the same as with the Musiland 01 MINI board.
Just like with the Musiland board, I was able to eliminate most of the dropouts by setting the DPLL bandwidth to “Medium-Low”.
Additionally, like when using the Musiland board, , the dropouts are much worse, when the DAC is first powered on. As the DAC “warms up”, the number of dropouts becomes smaller until reaching a steady state (about 15 minutes).
PCM2707 USB INTERFACE
I also have a PCM2707 based USB board. This is the “workhorse” of the Audio USB interfaces and it is implemented in many, many different designs. The downside is the 48KHz limit.
This device has been getting a bad rap lately with the introduction of “asynchronous” USB devices that can handle sample rates higher than 48KHz. Even though in the beginning it was praised, some measurements have put the jitter in the thousands of pico-seconds. Oddly, Stereophile measured the jitter of the Apple Airport Express at 258 ps which was likely based on the PCM270x devices (Newer versions are based on different spdif devices which may or may not improve jitter -likely not improve)
The datasheet says that it “employs SpAct™ architecture, TI’s unique system that recovers the audio clock from USB packet data. On-chip analog PLLs with SpAct enable playback with low clock jitter”. SpAct refers to a method of capturing the data from the usb isochronous (bursty) transfer in such a way that data is always ready to be transmitted in real time through the i2s or spdif interface. This means that SpAct prevents data transfer hiccups at the USB side and the PLL generates the clock for the SPDIF/I2S side. Thus the jitter of this device is determined by the quality of the (analog) PLL.
The implementation I used was the gamma1 board from AMB, populated just for the USB to I2S functionality and bus powered. This is as minimalist as you can get for a USB to I2S interface.
One surprising result is that this is the only interface (of the 3 I’ve tested) with an exact clock frequency of 44100 Hz
Surprisingly, after the “warm-up” period of the DAC, this interface behaves the same as the other interfaces: just like with the Musiland and OPUS boards, I was able to eliminate most of the dropouts by setting the DPLL bandwidth to “Medium-Low”. “Eliminating most” doesn’t mean completely eliminating. Like the other boards, once in while you will experience a dropout; and like the other boards, setting the DPLL bandwidth to “best” solved the drop-out problem.
NOTE: I didn’t spend enough time time listening with this board to determine exactly if it was “exactly” as the other boards, but within the time spend listening to this board, it seems the infrequent unlocks (with DPLL BW set to “Mid-Low”) was “a bit worse” than with the other boards. Maybe if I spend more time I would determine if it is worse than the other two interface boards, but for now I would say that it is “the same” as the other two boards.
I would say that without some good A/B comparison, the three interfaces sound pretty much the same with the PCM2707 seemingly the worse of the three and the Musiland I2S seemingly the best (Can’t really tell for sure but that would take some serious A/B listening and have not done that yet). For now I will use Musiland SPDIF output primarily because I can set the DPLL bandwidth to “lowest” which in theory rejects the most jitter.
Based on these testing, the information that has been shared in the diyaudio boards and the fact that there exist a 128x setting for the DPLL bandwidth, tt seems that the low settings in the DPLL bandwidth were not meant for real life applications.
The SPDIF can easily lock into a signal perhaps because it is locking to the preamble (the preamble tells you the start of a data block) as the Cirrus receivers have started to do.
In any case, in order to get the most out of the Sabre32 DAC one has to set the optimal DPLL bandwidth depending on the type of the incoming signal: “lowest” for spdif, “best” for i2s/dsd. This can be automatically done by detecting the type of signal in the status register. I’ve done exactly that in my code. And having a manual mode will allow additional optimization depending on the source.