Sabre DAC Datasheet: The Missing Parts

Now that I’m familiar with the Sabre datasheet and developed some code, I took a closer look at the long Sabre DAC thread at diyaudio. (over 1700 posts).

Before I had no idea about what they were talking about :-).  I have summarized some datasheet-relevant information here for my own benefit and for those who are thinking of programming the DAC

PIN DEFINITION

• Pin 8: Reset: 125
• Pin wiring to support Stereo and DSD-I2S-SPDIF: 145, 153
• Pin wiring to support I2S: 147

REGISTER DEFINITION

• Register 0-8, volume: 113
• Register 8, 18 Switching input format on the fly: 125
• Register 10 Jitter ON/OFF: 492
• Register 11 DPLL bandwidth: 575, 821
• Register 12, notch delay: 497, 758, 1315
• Register 14 DAC source: 153
• Register 14 true/pseudo diff (bit 3): 1683
• Register 14 IIR filter: 229, 2?
• Register 15 quantizer  35 and here
• Register 16 Automute: 159
• Register 17 Oversample bypass: 1279
• Register 37-45: Programmable filters: 1289

DEVICE CHARACTERISTICS

• Output impdeance, each output pin: 114
• Change Input Format (SPDIF-I2S-DSD) on the fly: 125
• Choice of clock frequency: 127
• External oversampling: 241
• Jitter Eliminator corner frequency: 320
• Jitter performance (vs other DACs): 385
• DPLL bandwidth compared 9018 vs 9008: 1256
• DAC design priorities: 388
• Digital Volume Control: 456
• Filter passband ripple: 496
• Input levels and switching frequency: 574
• I2S bitclock requirement: 1578
• DAC SNR and THD Spec: 1532
• Built-in FIR filter characteristics: 241, 1295

DEVICE ARCHITECTURE

• Volume Control is done before Oversampling Filter: 113, 456
• Oversample Filter -> Noise Shaper -> Jitter Reduction: 258
• Inputs to DACs 3, 4, 7, 8 can be tied to inputs to DACs 1, 2, 5, 6 respectively: 153
• DAC internal data path (ES9008): 254
• DPLL uses (locks to) bit-clock: 1626
• Data reclocking: 319

INTELLECTUAL PROPERTY (PATENTS)

• Asynchronous sample rate correction by time domain interpolation
• System and method for digital volume control
• Device and method for signal processing 
• Asynchronous Sample Rate Converter
• Low Noise Digital to Analog Converter with Audio Applications
• Low noise digital to signal interval converter with audio applications

PRESENTATIONS

• High End Audio DACs

OTHER

• Buffalo DAC I Schematic: 189
• White Paper: ESSTech
• Experimental Results on best DPLL settings: 1853

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