R-2R DAC For The REST of US

A MOST INTERESTING DIY PROJECT IN A LONG TIME

A Discrete R-2R Sign Magnitude 24 bit 384 Khz DAC [link].

The DAC Module includes all local power supplies, a programmable low jitter clock, Micro-controller and balanced output buffer. It is implemented on a 4-layer PCB. The board size is 3.2″ x 5.8″ (81 x 147 mm).

As the industry migrated from R2R topologies to Sigma-Delta in their quest for higher bit-depth, higher performance (and cost management), present implementations of R2R DACs are pretty much hand-crafted commanding a high premium.

As the author states:

“I believe that the sound quality will be the absolute best, better than any Delta Sigma DAC, in class with discrete DAC’s from totaldac and msb technology. And for way way less cost :-)”

For the rest of us with limited resources wanting to experience a ladder DAC, this is the DAC to have.

An excerpt from the PCM1704 [link] datasheet expunds the good points of a ladder DAC:

Digital audio systems have traditionally used laser-trimmed, current-source DACs in order to achieve sufficient accuracy.

However, even the best of these suffer from potential low-level non-linearity due to errors in the major carry bipolar zero transition. Current systems have turned to oversampling data converters, such as the popular delta-sigma architectures, to correct the linearity problems. This is done, however, at the expense of signal-to-noise performance, and the noise shaping techniques utilized by these converters creates a considerable amount of out-of-band noise. If the outputs are not properly filtered, dynamic performance of the overall system will be adversely effected.

The PCM1704 employs an innovative architecture which combines the advantages of traditional DACs (e.g., excellent full-scale performance, high signal-to-noise ratio, and ease of use) with superior low-level performance.

Granted, that was circa 1999. Since then the Sigma-Delta camp has made great strides. Even so, R2R DACs have not lost their appeal as witnessed by the interest in this project and the current commercial offerings.

TARGET PRICE

The DAC module is not yet available for sale. The target price is US$240 with 0.02% resistors. This is a steal considering how much other R2R implementations cost.

ADVANCING THE STATE OF THE ART

The last commercially available R2R DAC chips were the PCM1704 [link] and the AD1865 [link]. They have been out of production for a long time but still available for purchase for example here [link] and here [link].

Here is a table comparing selected performance numbers and features as described in the data sheets and by the author in the diyaudio discussion thread.

• The PCM1704 is typically used withe a companion chip, the DF1704 [link].
• The AD1865 is also used with a companion filter chip such as the Sony CXD1244S [cxd1244s]

Parameter	Seokris R2R	PCM1704+DF1704	AD1865+Digital Filter
Max Input Sample Size	24bit	24bit	18bit
Max Input Sample Rate	382KHz	96KHz	44KHz
Max Resolution	28bit (1)	24bit	18bit
Inputs (2)	1x Isolated I2S, 3x SPDIF/TOSLINK/AES/EBU [link]; future DSD upgrade	Serial only (DF1704: LJ, I2S)	Serial only through the digital filter chip
S/W Interface	Serial (Not I2C)	Serial (Not I2C)	Depends on filter chip
Oversampling Filter	On-board built-in and user defined (3)	Sharp, Slow roll-off (DF1704)	Needs External Filter
Channels	2 – Stereo	PCM1704 is single channel, so DF1704+2XPCM1704	2 – Stereo
Jitter Reduction	Re-clocking input data through a FIFO Buffer (similar in design to Ian’s FIFO [link]). Uses a low jitter (0.8 psec RMS) Si514 programmable clock [link] which drives the LVC595 shift registers after clock division in the FPGA (Si514 -> FPGA divider -> LVC595)	None	None
Output	“Raw” single-ended voltage output (1.4V RMS, 1.25 Kohm) or buffered balanced voltage output using TI LME49710 + LME49724 [link]	Single-ended current output	Single-ended current output or buffered single-ended voltage output
Jitter Reduction	FIFO Buffer and reclock with low jitter clock	None	None
THD+N (0db)	0.0063% .05% resistors (Module measurement)	0.0008% K-Grade (PCM1704 spec)	0.003% J/K Grade (AD1865 spec)
THD+N (-20db)	–	0.006% K-Grade (PCM1704 spec)	0.01% J/K Grade (AD1865 spec)
THD+N (-60db)	0.37% .05% resistors (Module measurement)	–	1% J/K Grade (AD1865 spec)
SNR	126 dB (Link)	120 dB	110 dB

Notes

(1) The Soekris R2R implements 28 bits of internal resolution in order to provide sufficient headroom to allow for a “perfect digital volume control. At -72 db volume you still have 16 bit resolution with perfect linearity” [link].

(2) The PCM1704 and AD1865 are NOS ladder DACs expecting an input stream from an external filter device such as the DF1704 [link]. Therefore they typically cannot accept and I2S input format. The input format for those chips consists of a clock signal, data signal and data latch signal. More information can be found in Ian’s “I2S to PCM” board project [link].

(3) The oversampling filter is implemented in the on-board  Spartan-6 LX16 FPGA. It has 15K logic cells and can be configured as having 8 full high resolution MAC’s by using its 32 DSP48A1 MAC blocks in groups of 4 allowing them to do 35 x 35 bit multiplications plus 70 bit summers. Two of these hig-res MACs can be used  for the first 2 most critical oversampling FIR filters; running them at just 49.152 Mhz makes space for 1024 coefficients if needed, then 2 more for the rest of the FIR filters. The rest for other functions, like de-emphasis, volume control and digital crossover filters… [link]. The user can use generate the filter coefficients and upload them to the FPGA [link]

Filter tools:

• T-Filter [link]
• rePhase [link]

Here is a photo showing some of the details disclosed in the diyaudio thread. The LVC595A [link] are 8-bit shift registers: 7 bits on one side of the chip and the 8th bit on the other side of the chip. In this implementation the 8th bit is not used in order to optimize the layout (only using the outputs on one side of the chip) as can be seen in the photo.

The capacitor in the low pass filter (C142 in the photo) is the only capacitor in the signal path. It is a high quality C0G/NP0 ceramic. Those wishing for “higher quality” can replace/bypass with a film capacitor.

ISOLATED I2S and SPDIF INPUTS

The input is isolated with (what appears to be) TI ISO7420FE digital galvanic isolators [link]. There are 3 identical isolators resulting in 6 input lines. I think these support one I2S input and 3x SPDIF/TOSLINK/AES/EBU (I don’t know if the SPDIF lines are isolated, but there is no need for 6 isolated inputs if only the I2S is isolated). More info on isolators here [link]. Seems everyone has their favorite isolation device. Of the 4 different vendors I have surveyed, they have all been used by different audio diy implementers.

The TI ISO7420x and ISO7421x provide galvanic isolation up to 2500 V RMS for 1 minute per UL and 4242 V PK per VDE. These devices have two isolated channels. Each channel has a logic input and output buffer separated by a silicon dioxide (SiO 2 ) insulation barrier.

Built-in galvanic isolation at the input is a great idea. This gives the capability to completely isolate noise disturbance is coming from the source, including isolating ground, and since here is a FIFO reclocking stage afterwards, there is no need to worry about the small added jitter (100-200 psec RMS) that these devices would add to the data.

(update [link]) There will be two AES/Spdif inputs:

• Balanced into LVDS Receiver, can be connected directly to transformer and can be run single ended for SPDIF Coax, just a capacitor and two resistors needed when single ended 75R. To keep it isolated I recommend to always use a transformer for AES Balanced and SPDIF Single Ended inputs.
• 3.3V CMOS level input, can be connected directly to SPDIF Optical Toslink receiver.

Selection between I2S and AES/SPDIF sources can be automatic or manual with two pins that can be connected directly to a control switch. For more sources you can also just switch the inputs.

JITTER REDUCTION

A notable feature of this DAC module is the reclocking of the incoming. The design is similar in principle to Ian’s FIFO reclocker, The data is received into a configurable FIFO and then it is reclocked with a lower jitter clock.

However, Ian’s reclocker is designed for ultimate performance, whereas this reclocker is designed specifically for the DAC module and therefore matched to the requirements of the entire system (meaning, I think, the best consideration for jitter performance, cost and part count).

Here are the main differences between the two:

Ian’s FIFO reclocker

• Clock is Si570 which is the best programmable clock from Silicon Labs (.3 psec RMS jitter) [link]
• Clock drives the low jitter shift registers through a clock-fanout [link]. The jitter in the fan-out device is in the fsec range

Here is the clock board in Ian’s reclocker: the Si570 is used to clock the shift registers directly.  The clock connects to a fan-out device (the chip next to the clock) and separate clock lines drive the 3 shift registers in the middle of the board.

R2R Module reclocker

• Clock is Si514 is the lower grade of programmable clocks from Silicon Labs (.8 psec RMS jitter) [link]. This is used instead of the Si570 because of power consumption (lower consumption for the Si514)
• Clock signal is transmitted through the FPGA for clock division and then to the shift registers. The added jitter in the FPGA is in the psec range. More details on the jitter through the FPGA here [link]

Here is the Si514 feeding its clock to the FPGA. The FPGA supplies the clock to the shift registers.

However, the reclocked signal in the R2R module feeds straight through the resistor ladder avoiding “several layers” of electronics as compared to a conventional implementation where the reclocked signal feeds the I2S receiver, the internal filters and other electronics of DAC chip. Internally, these “several layers” of electronics add jitter to the signal before arriving to the D/A conversion stage.

In the end, the actual jitter as seen by the resistor ladder is the cumulative jitter consisting of following components

• Clock intrinsic jitter (0.8 psec RMS)
• Jitter added by the FPGA (I think in the order of 10s psec RMS based on datasheet numbers)
• Jitter added by the shift registers in the psec order based on general data on shift registers

10s of psec RMS jitter at the resistor ladder is pretty darn good in my opinion.

Further details [link]

The details of my clocking/FIFO:

Ian’s FIFO use a fixed clock, and therefore use a large buffer to take up the difference between incoming and outgoing clock. That add a large delay, which doesn’t matter for simple audio applications but are undesirable in a number of applications, like home theater or live music.

I use a much shorter FIFO, selectable down to 1 mS, and instead adjust the outgoing clock to match the incoming clock frequency as needed, being I2S or SPDIF. The Si514 oscillator used is very low jitter and digitally programmable with a resolution of 0.026 ppb (parts per billion, not million…). It also have the feature that reprogramming inside +-1000 ppm is glitchless, ie the clock adjust very nicely to small changes.

ON-BOARD MICROPROCESSOR

The onboard microprocessor is the STM32F030 uC [link]. It is responsible for:

• Measure input clock and program the Si514 programmable clock as needed
• Initially, volume control by using a potentiometer
• More features later since this is a general purpose uC

The specific device is the 32 pin device of the family with 16 general I/O pins. I believe some of the I/O pins are available through J1

POWER SECTION

The following details have been shared about the power section of the DAC ([link], [link], [link])

• Designed to be powered by a single dual 7-8V, 5W transformer. Can also take an external +/- 7-15V DC supply. Filter capacitors are Nichicon 820uF 16V CL series
• “The LME output buffers are powered via an additional large RC filter after the main capacitors, no active regulators. With a typical PSRR of 125 db I didn’t worry much about 100/120 hz ripple, only worried about higher frequency noise on the power rails….”
• A DC-DC converter (switch mode) provides the 1.2V for the FPGA core. Every other supply is low noise linear [link]
• The most critical supply is the +/- 4V reference for the resistor ladder.  This is generated by a “two step, first to +- 5V, then to +-4V by precision low noise medium current opamps”; “-4V reference is sent though an inverter with 0.01% resistors generating the +4 reference”. The references are further  “filtered and buffered for each rail and channel”.
• Negative voltage is required for the output opamps and other parts of the circuit [link]

Here is a picture of the main supply section. The description is my best guess based on the information provided. I believe the digital section is powered by a DC-DC converter-regulator, except for the clock which has its own regulator.

CUSTOM FILTERS AND DIGITAL CROSSOVER

I think the ability for user-defined custom digital filters is a BIG feature for this DAC. In addition to the traditional DAC filters, one can load filters that implement crossover functions.

One of my frustrations with the ESS DAC is that I have not been able to take advantage of the custom filter facility. I am able to program everything else, except for the custom filters. Even though some claim that this feature works fine, I have not encountered any diy implementation and only one or two commercial implementations. Whether due to my own ignorance or to other factors (such as lacking documentation), fact is that there are no publicly disclosed diy successes of having implemented custom filters in the ESS DACs.

With crossover filters, there is finally a BIT PERFECT high quality DAC + digital crossover solution. More specifically, current digital crossovers if used with an external DAC of choice would add additional A/D or D/A conversions plus asynchronous sample rate conversion. Imagine a more “straight wire” implementation.

(Update [link]):

First firmware release will NOT support digital crossovers, although there will be 14 available biquads, already tested in order to support de-emphasis on SPDIF inputs. As somebody already noted, there is issue of syncronization…. I have a couple of ideas how to connect multiple boards together, but I don’t have time to implement and test before shipping the first batch. But as I already said, all firmware on the board is upgradable though a std PC serial port, I will implement it soon as my big speakers are already designed for electronic crossover use….