Amanero Reclocking: 352.8K/384K
(1/28/13) Important Update: See comments section regarding reclocking with the DACs 100 MHz clock.
Even though the Amanero USB interface supports 352/384K sampe rates, if this high sample rate bitclock is reclocked with the original clock signal, the output is completely silent The DAC cannot see a signal to lock on. Here is the reason why:
Here is the truth table of a flip flop: the output (Q) reflects the input (D) on the rising edge of the clock (CLK) signal.
Here is a diagram illustrating the re-clocking of two signals: a 175.4 KHz sample rate signal and a 352.8 KHz sample rate signal. Keep in mind that at 352K sample rate, the frequency of the bit clock is the same as the frequency of the 22.5792 MHz on-board clock. (352.8K x 64).
Shown in red is the clock signal taken straight from the clock and fed to the flip-flop. In gray are the input signals coming from the CPLD and fed to the flip-flop. Since there is a propagation delay in the CPLD, they are shown with a delay in relation with the native clock signal. In green is the output from the flip-flop.
If we follow the truth table above, we can see that at 176.6K, the output can still follow the input but with the edges coinciding with the edges of the original clock signal. But with the 352K signal, we see that at the rising edge of the original clock signal, the input is always at the same value, hence the flat output.
At 352K, the Buffalo DAC correctly reports “No Lock”. Indeed, there is no signal to lock to.
Thus if using reclocking with the original clock signal, you will loose the ability to play 352k/384K, unless Amanero releases a new board with clocks with frequencies 2X the current values, or you manually bypass the reclocking flip-flop.
Rather than reclocking with the “source clock”, one can reclock with the “destination clock”. Russ has experimented with reclocking the I2S lines with the Buffalo 100 MHz clock (see comments below) with good results. Reclocking with the destination clock (the clock of the Buffalo DAC) would require reclocking all 3 I2S signal lines to ensure bit-perfectness.
“Destination clock” only applies to DACs that normally operate in asynchronous mode, generating their own clocks. I think only the ESS DACs would operate in this manner. Most other DACs require a master clock as required input.
The circuit, with Potato flip-flops would look something like this.