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Amanero Reclocking: 352.8K/384K

December 1, 2012 Leave a comment Go to comments

(1/28/13) Important Update: See comments section regarding reclocking with the DACs 100 MHz clock.

Even though the Amanero USBΒ  interface supports 352/384K sampe rates, if this high sample rate bitclock is reclocked with the original clock signal, the output is completely silent The DAC cannot see a signal to lock on. Here is the reason why:

Here is the truth table of a flip flop: the output (Q) reflects the input (D) on the rising edge of the clock (CLK) signal.

Truth2

Here is a diagram illustrating the re-clocking of two signals: a 175.4 KHz sample rate signal and a 352.8 KHz sample rate signal. Keep in mind that at 352K sample rate, the frequency of the bit clock is the same as the frequency of the 22.5792 MHz on-board clock. (352.8K x 64).

Shown in red is the clock signal taken straight from the clock and fed to the flip-flop. In gray are the input signals coming from the CPLD and fed to the flip-flop. Since there is a propagation delay in the CPLD, they are shown with a delay in relation with the native clock signal. In green is the output from the flip-flop.

If we follow the truth table above, we can see that at 176.6K, the output can still follow the input but with the edges coinciding with the edges of the original clock signal. But with the 352K signal, we see that at the rising edge of the original clock signal, the input is always at the same value, hence the flat output.

reclock

At 352K, the Buffalo DAC correctly reports “No Lock”. Indeed, there is no signal to lock to.

Thus if using reclocking with the original clock signal, you will loose the ability to play 352k/384K, unless Amanero releases a new board with clocks with frequencies 2X the current values, or you manually bypass the reclocking flip-flop.

ANOTHER WAY

Rather than reclocking with the “source clock”, one can reclock with the “destination clock”. Russ has experimented with reclocking the I2S lines with the Buffalo 100 MHz clock (see comments below) with good results. Reclocking with the destination clock (the clock of the Buffalo DAC) would require reclocking all 3 I2S signal lines to ensure bit-perfectness.

“Destination clock” only applies to DACs that normally operate in asynchronous mode, generating their own clocks. I think only the ESS DACs would operate in this manner. Most other DACs require a master clock as required input.

The circuit, with Potato flip-flops would look something like this.

BReclock

  1. Zoran
    December 1, 2012 at 11:32

    delay the MCK, and invert before the input to the flip flop…
    Or just try to invert the MCK signal before the input to flipflop
    inverter will add some little delay. try to measure what is exact delay
    and find the inverter with this dt for this Fo…
    cheers

    • BlgGear
      December 1, 2012 at 17:17

      Hi Zoran, thanks for the comment.

      I tried the Q-bar output of the flip-flop (inverted) and that killed 192KHz signals.

      In any case, I think even if I can align the clock to the signal, they being of the same frequency would violate the minimum timing requirements of setting and hold. The second point is that adding additional circuitry to the original clock signal (plus all the wiring) would increase the jitter, which defeats the purpose of using the original clock for reclocking. The goal was to add the minimum possible circuitry and thus add the minimum possible amount of jitter to the clock signal.

  2. qusp
    December 1, 2012 at 14:18

    well if running synchronously and with oversampling enabled on the ess, the clock obviously isnt fast enough for these high speeds anyway.

    • BlgGear
      December 1, 2012 at 17:17

      Hi qusp,

      That is true. I was expecting noise, but not silence :-). But a 2x clock in the Amanero, proper terminals and a well designed reclock board would result in a pretty good interface

  3. 2a3set
    December 2, 2012 at 02:45

    you can do with a frequency doubler with a buffer + RC delay and XOR gate (po74g86a), please check reference circuit at,

    http://www.diyaudio.com/forums/digital-line-level/79452-building-ultimate-nos-dac-using-tda1541a-190.html#post1461029

  4. qusp
    December 2, 2012 at 07:11

    I agree its not a bad little board at all, i’m not going to spend much time tweaking it at the moment though, I only got it to do a few DSD experiments, I need the multichannel features of titan going forward, while i’m still completing the rest of my system its something to play with though.

  5. David Quayle
    December 2, 2012 at 08:35

    I have to ask this question as I know VERY little about this subject.

    Why are you reclocking?

  6. David Quayle
    December 2, 2012 at 21:31

    Thanks, It seems your remark about “it may not work” was appropriate.

  7. Zoran
    December 3, 2012 at 09:40

    if You using just one stage flipflop that will “delay” signal for 1/2 of MCK period
    and the signals will be “re-clocked” but with “opposite phase”
    or more true with the falling edge of the mck, which is different that input and output stage desired? If You use 2 x flip flop (google for Metastabile…)
    You will have reclocked but with the rising edge of the MCK
    .
    Use fast FF (potato is very good)
    and check for the signal integrity too (google)
    cheers

    • BlgGear
      December 3, 2012 at 21:03

      Thanks. I’ll need to think through this some more (to understand what you are saying :-))

  8. December 3, 2012 at 19:34

    One thing I have briefly done as a test is use a flip-flop where the clock input was the 100Mhz master clock from the DAC. I then ran my PCM/DSD signals through that – which basically just time aligns the PCM/DSD signal edges exactly with the on-board master clock. It worked very well. Internally the DAC has to basically do the same sort of thing via the DPLL. This just makes it much easier on the DPLL. I am not sure if there were any negative effects, I sure couldn’t detect any – the result sounds excellent.

    It is a very simple thing to do. Well worth a shot.

    The B3SE makes the very easy with it’s master clock header and uFL connector from which you can feed the flip-flop.

    Cheers!
    Russ

    • BlgGear
      December 3, 2012 at 21:08

      Hmm, that would be very interesting It would probably eliminate all the unlocks because it is driven by the same clock, going through the same warm up and variations. What flip-flop did you use?

      However, I wonder if it is always “bit-perfect” especially at higher sample rates…

  9. Russ White.
    December 3, 2012 at 22:02

    I used the potato ghz type.

    Yes it would still be bit perfect, just with the signals aligned to the master clock.

  10. Russ White.
    December 3, 2012 at 22:04

    Used 2 duals on a simple DIY single side PCB. Of course one channel was simply not used and the input pulled to GND.

  11. Russ White.
    December 3, 2012 at 22:07

    To be clear – you would definitely want to give all three i2S signals the same treatment to keep things truly in synch. In this way the DATA and bit clock edges are always in synch, and the data will be accurate.

    • BlgGear
      December 4, 2012 at 00:38

      Worth trying!. I was looking at a tri or quad flip flip from Potato, but not available.

  12. Russ White.
    December 4, 2012 at 01:55

    You need two duals. πŸ™‚ With one channel simply connected to GND at the input. Yes too bad they don’t make a single or a quad.

  13. David Quayle
    December 4, 2012 at 02:24

    russwyte :
    One thing I have briefly done as a test is use a flip-flop where the clock input was the 100Mhz master clock from the DAC. I then ran my PCM/DSD signals through that – which basically just time aligns the PCM/DSD signal edges exactly with the on-board master clock. It worked very well. Internally the DAC has to basically do the same sort of thing via the DPLL. This just makes it much easier on the DPLL. I am not sure if there were any negative effects, I sure couldn’t detect any – the result sounds excellent.
    It is a very simple thing to do. Well worth a shot.
    The B3SE makes the very easy with it’s master clock header and uFL connector from which you can feed the flip-flop.
    Cheers!
    Russ

    Do you have any info (drawing) of how this would be implemented I have limited knowledge and me trying to fill in the gaps would be dangerous.

    I am waiting for my B3SE to arrive and am keen to implement Amanero etc when it does.

    • BlgGear
      December 4, 2012 at 07:26

      I’ve added a diagram to the post… The key is to have a good layout…

      • David Quayle
        December 4, 2012 at 09:14

        BlgGear :
        I’ve added a diagram to the post… The key is to have a good layout…

        Thank you.

        Is it worth trying to power the Amanero from something other than its USB input? I’m trying to workout if I need to squeeze anything else into the case (like another regulator or power supply) before I build it.

  14. December 4, 2012 at 13:11

    The diagram looks correct to me, and in fact I would definitely. I like especially that you indicated the FF with the bit-clock as the one with the unused channel. That will help keep that signal a bit cleaner.

    • BlgGear
      December 4, 2012 at 21:00

      Hi Russ, thanks for checking it out. Did you build a PCB for your prototype? We are dealing with high frequency clock, power, gnd and signal. I think layout will have a lot of effect on the implementation.

  15. David Quayle
    December 4, 2012 at 21:15

    BlgGear :
    Hi Russ, thanks for checking it out. Did you build a PCB for your prototype? We are dealing with high frequency clock, power, gnd and signal. I think layout will have a lot of effect on the implementation.

    Do you mean soldering a few wires around the place wont do the trick 😦

    • BlgGear
      December 5, 2012 at 04:16

      I am trying to keep the diyaudio police away πŸ™‚

  16. Russ White.
    December 4, 2012 at 21:58

    I did make a little DIY PCB – but honestly a good proto-board like the one you used should work sufficiently well. πŸ™‚ Just bypass the supply pins well.

  17. David Quayle
    December 5, 2012 at 09:28

    Russ White. :
    I did make a little DIY PCB – but honestly a good proto-board like the one you used should work sufficiently well. Just bypass the supply pins well.

    At every point of connection, 2CLR, 2 PRE etc or just at just Vcc. I’m going to try & design a PCB which should cause a few laughs πŸ™‚

    • BlgGear
      December 5, 2012 at 18:52

      VCC only

  18. December 5, 2012 at 16:13

    I want to carefully state – that while it worked, and the sound was good – I am not at all ready to state the synching the edges to the 100Mhz is “better” – I just wanted to see if it would work, and it did. And it sounded good to me. πŸ˜€ I just wanted to see if anyone else was interested in trying it and see if their result was the same as mine. This is a highly experimental exercise.

    • BlgGear
      December 5, 2012 at 19:06

      The alignment of the PCM edge with the 100 MHz clock results in PWM at some frequency. I wonder what is the theoretical effect of a PCM signal with some PWM on its pulses…

  19. December 5, 2012 at 19:53

    It’s a good question. My understanding though (limited as it is) is that it should not have a profound impact. Still I would love if someone would actually measure it. πŸ™‚

    • BlgGear
      December 6, 2012 at 06:21

      I’ll order some more potato flip flops and try it out. Have you tried their quad MUX for switching sources?

  20. Russ White.
    December 6, 2012 at 11:27

    I have something even better for that. πŸ™‚

  21. December 6, 2012 at 13:21

    In direct answer to your question, yes, I have looked at them. They are nice, it’s just the best ones have 3.6V max voltage which is actually not ideal for our situation. I prefer the BUS switches that have a VCC max of 6V. The reason is that the more headroom you give the switch, the better the waveform looks coming out. So even if the signal is LVTTL you benefit from the headoom. You also avoid potentially needing another regulator.

    Still I have not completely ruled them out.

  22. December 6, 2012 at 20:43

    We already have one of those. the only think I don’t like about it is the 3.6V restriction.

    • BlgGear
      December 6, 2012 at 21:36

      I see what you mean now. Power the bus switch with 5V (taken from the Placid/input voltage to the DAC) but feed LVTTL. Also you like to power the potato with 3.6V instead of tapping existing 3.3V from the DAC.

      But: Doesn’t the low noise approach of the Potato part make up for the lack of headroom?. Seems their approach tends to minimize added jitter.

  23. Russ White.
    December 6, 2012 at 22:04

    It not really about jitter – not that sort of noise.

    But yes – I am sure at 1-2Ghz the potato part would be a much better choice. πŸ™‚

  24. Russ White.
    December 6, 2012 at 22:10

    Also – to be more clear, once the bus switch is switched – that sort of noise does not really come into play. When constantly on a switched FET simply looks like a very low value resistor – basically like a closed relay. πŸ™‚

    Now if you were constantly switching the switch to create a signal (which some application do) – then you would care more. That is the kind of noise the potato part would handle better, but in this (OTTO-II) application the switching only occurs when you change sources. πŸ™‚

  25. David Quayle
    December 16, 2012 at 09:07

    I have a spare Placid 2.0.1 laying around & was thinking of using it to power the Amanero & then using the 3.3v out of the Amanero to power the Flip Flops as shown above. I am going to power 1 Placid HD For the BIIISE & the other Placid off 1 of the 9V + 9V 15VA TP transformers.

    Do you see any issues with this approach?

    What would be the best location to attach the power to the Amanero?

    • BlgGear
      December 16, 2012 at 23:03

      IMO overkill, but should be OK ;-). The best place to apply the 5V is from the cable: Cut the 5V an provide the new 5V. The Gnd must remain connected to the source (computer), so just connect the gnd of the placid to the wire

  26. David Quayle
    December 17, 2012 at 02:12

    BlgGear :
    IMO overkill, but should be OK . The best place to apply the 5V is from the cable: Cut the 5V an provide the new 5V. The Gnd must remain connected to the source (computer), so just connect the gnd of the placid to the wire

    I’m assuming you mean by overkill is that you are happy just powering the Amanero from the computer?

    If that is the case sounds good to me. Will that work with an Ipad, which I don’t own yet?

    • BlgGear
      December 17, 2012 at 07:14

      Noise will also sneak through the signal lines and gnd. Currently there are no isolators fast enough to isolate usb2

  27. David Quayle
    December 18, 2012 at 11:29

    OMG the flip flops are miniscule, soldering should be fun.

  28. January 28, 2013 at 18:27

    A quick update – I will state up front – I was completely wrong. πŸ™‚

    I found the re-clocking via flip flop to the 100Mhz clock was actually destructive to a jittery signal. Not in the way you might think. It actually can cause a very slight error in the data. It definitely will not help. Someone called this a decimation error, but I am not sure that is the correct term.

    After a while I noticed that the sound was actually worse… less precise, kinda murky. It sounded like jitter… ouch.

    This is because the original bit clock reference which the ES9018 uses to tune the DPLL is completely lost. It becomes “aliased” or maksed if you will with the master clock.. In other words It sees the damaged data as perfectly good defeating the super cool algorithm ESS designed to fix jitter… yikes not what we wanted at all now is it.

    This mod makes it super easy for the DAC to lock, but now every 20 or so samples (I am not sure exactly how many – it depends on the rate) the data contains errors.. bummer. We shifted clock errors into the data domain… Only now – to our dismay – the DPLL is missing the source clock context it needs to *fix* the data! Bummer. We effectively defeat the DAC at one of the things it does best, Rejecting jitter. 😦

    If you refer to the ESS DPLL/ASRC patents it starts to make perfect sense.

    Further – It was explained to me that the idea itself completely redundant. The reason is that the DAC *already* time aligns all inputs with the master clock during the process of re-sampling. and even better when it re-samples it does so in a loss-less way. You cannot make the flip flip circuit loss-less – thus the data error.

    So chalk it it up to a fun, but tragically failed experiment. A valuable lesson learned. πŸ™‚

    It was an interesting idea, but alas, not a good one. My advice is to feed the signal to the DAC – and let it do what it does best. Don’t try to fix what ain’t broke.

    This video gives a good glimpse into why such a mod is redundant:

    It also very interesting in regard to digital volume control.

    Yes! Analog is technically better , but only if your implementation can manage a -133db noise floor. πŸ™‚ Good luck with that. It highlights just how good the volume control (and analog noise floor) of the ES9018 actually is.

    Other DAC chips would be far better candidates for various re-clocking schemes.

    Cheers!
    Russ

    • BlgGear
      January 28, 2013 at 19:25

      Hi Russ,

      Thanks so much for the update. Yeah, I think mentally the picture was that the new data was “pulse modulated” with the reclocking frequency (the 100 MHz clock) and how would the chip respond to that.

  29. Outre
    September 28, 2014 at 19:22

    Hi guys,

    I wonder if I get extra benefit like “balanced signal” with re-clocking in order to use those Potato flip-flops. Can I use Potato chip’s Q-bar pin for getting inverted signal at same time?

    I need additional inverted i2s signal from my amanero but I don’t know how to do it.

    Thanks.

    • BlgGear
      September 29, 2014 at 17:25

      Balanced signals are for noise immunity especially for transmission at long distances. I doubt there is any benefit for local transmission. In addition, the DACs don’t take “balanced signals”

      • Outre
        October 1, 2014 at 18:21

        If you want to use a line level transformer at dac output, or if you need more swing than single dac’s specification balanced signal does matter. It is not about long wire. It is about how you want to deal with analog signal.

      • Outre
        October 1, 2014 at 18:24

        Additionally, dac’s don’t take “balanced signals” of course. Dac’s take only bits.. than I need inverted bits in order to get inverted signal.

      • BlgGear
        October 1, 2014 at 22:47

        Hmmm, do you mean feeding the inverted I2S to a second DAC? I don’t think you will get an inverted signal on the second DAC, you will get the same signal

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