Here is an implementation of synchronous reclocking the I2S signal in the Amanero board reported on diyaudio:
After improvement of getting MCLK from XO instead of using standard PIN 6, I tried reclocking the BCK with same MCLK and the improvement is very positive. Right now I tied PIN43/44 on CPLD together, fed MCLK to reclocker and DAC with 2K resistor. The reclocker is 74AUC1G74 D-type flip-flop at 2.5V (power pull from 3.3V with 330ohm in series). Left side is PCM5102 DAC
The basic idea is to:
- Feed the oscillator clock signal directly to the DAC
- Use the oscillator clock signal to drive a flip flop which reclocks the Bit Clock
This reclocking scheme can be done with any USB-I2S where you can tap a low jitter clock signal. Typically these are the ones that derive the clocks from oscillators rather than internally by the FPGA. A good candidate is Lorien’s XMOS-based WAVE IO
The goal is to reduce jitter in the I2S signals, including the master clock by leveraging the fact that the jitter added by a flip flop is much less than the jitter added by a CPLD or FPGA.
Even thought the on-board oscillators are low jitter, the signals coming out of the CPLD have a minimum amount of jitter in the order of 100 psec peak to peak. If we take the master clock straight from the oscillator rather than from the CPLD, we don’t have the added jitter by the CPLD. If we also use this clock signal straight from the oscillator and re clock the bit clock, then this new bit clock will also be of lower jitter than the original bit clock coming out of the CPLD.
HOW DOES IT WORK?
“When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse.”
Here is a logic table for a typical flip-flop (this one taken from Potato Semi 74G74 datasheet)
Basically, the flip-flop re-aligns the edges of the bit clock to the edges of the master clock. From the above table, rows 4 and 5, D (data input) is reflected at Q (output) on the rising edge of the CLK (clock). Thus if we use the clock signal directly from the oscillator (low jitter), and feed the bit clock from the CPLD to the D input of the flip flop, it will be “reclocked” resulting in a lower jitter signal at Q (output)
RECLOCK LR CLOCK AND DATA?
Data is read in reference to the bit clock. As long as the minimum timing requirements are met (set up and hold times), a value of 1 will be read as 1 and a value of zero will be read as zero. It is probably safe to assume that systems are designed with sufficient timing margin that even with a more jittery bit clock, there are no digital errors. Therefore, there is no need to reclock the LR clock and the DATA
WHAT ABOUT TIMING?
There are some timing considerations we need to think about with regard to this manner of reclocking. The master clock coming out of the CPLD is synchronized with the other I2S signals (Bit clock, LR clock and Data). In comparison to the clock signal at the oscillator output (oscillator clock), these signals have a certain amount of propagation delay just for the fact that they have gone through the CPLD device. I am not exactly sure how much is the propagation on the output signals, but based on the CPLD datasheet, it may be in the order of 10 (or 10s) nano-seconds.
When the bit clock is reclocked with the oscillator clock, the new reclocked bit clock will be further delayed because it would have likely missed the rising edge of the oscillator clock (the signals out of the CPLD are delayed by the propagation delay) and would have to wait for the next rising edge of the clock signal.
How much is the bit clock delayed?
As discussed, the flip flop aligns the new bit clock to the rising edge of the oscillator clock. The oscillator clock is ahead (timing wise) of the master clock to which the bit clock is synchronized. The bit clock would have likely missed the rising edge of the oscillator clock and needs to wait for the next rising edge of the oscillator clock. The resulting new bit clock is thus delayed ONE PERIOD time of the oscillator clock. (It could be half a clock period depending how the signals are synchronized to the master clock: rising or falling clock edge)
One period for a 22.5792 MHz clock is 44 nsec. The bit clock for 44.1 KHz material is 354 nsec. The potential maximum delay of the new bit clock is a small percentage of the width of the bit clock which in this case is 44/354=12%. There should be no problems as also reported working by the poster above.
However, for higher sample frequencies, the delay becomes a larger percentage of the bit clock width. If we look at 172K material, the bit clock period is 88 nsec and the delay in the new reclocked bit clock is 50%. Perhaps this will still work. Increasing the sample rate further, say 352K sample rate, the delay is the same as the width of the bit clock. This will result in completely missing the first bit of the data signal.
- The Experimenter above uses 74AUC1G74 D-type flip-flop (operates at 1.8v)
- A better fit with 3.3V operation is the SN74AUP1G74
- Also recommended in the forums with even wider operating voltage: 74VHC74
- This flip flop is used in Ian’s FIFO Clock board (3.3v operation): 74AUP1G79
- Potato Semiconductor 74 Series Logic: PO74G74A. Extremely fast and very low propagation delay.
Some would argue that because the Potato Semi device is the fastest device, the added jitter is smallest. This would make sense. The technology used by Potato Semi in their devices are based on noise reduction which helps reduce jitter.
WHO IS POTATO SEMICONDUCTOR?
Based on the funky name, company log0 and the bare design of their website, Potato Semi seems a company of dubious reputation. However this is a company that have invented some cool technology. Here is the invention if you are interested in reading patents [link].
According to the press:
Potato Semiconductor, a leading IC design company focusing on the high speed CMOS I/O field, has successfully applied its innovative technology to 74 series logic ICs. Using advanced technology, this new generation of 74 series logic ICs features high performance, high frequency and low noise. The running speed can be 5 to 7 times faster than existing 74 series ICs which continues the prevailing trend in electronics design — high speed and high performance.
But the strongest vote of confidence comes form Ian’s FIFO reclocker. He has experimented with Potato Semi chips and has selected it for his latest clock board [link].
The chip can be purchased direct through eBay for $3. Not cheap in comparison with standard logic chips which cost in the order of $0.50. But for a few bucks you can (theoretically) drastically reduce the output jitter of the Amanero board (or other interface with similar design)
INTERFACING TO BUFFALO DAC
The synchronous reclocking approach described here seems ideal for interfacing with the Sabre DACs for the following two reasons:
- The oscillator frequency of Amanero (22.5792 MHz and 24.576 MHz) is below what the Buffalo DAC considers “normal” which is higher than 40 MHz. So the best way is to operate the DAC in its normal asynchronous mode, taking advantage of the DAC’s local oscillator
- The DAC locks to the bit clock, therefore it is desirable to generate a low jitter bit clock with this method of using a flip flop driven by a low jitter oscillator clock
- Reduce jitter to the absolute minimum possible with the board
- Easy to do, low cost
- May not work for higher sample frequencies
This would be a very nice and interesting (and very cheap) mod. Definitely worth trying it out. I’ve already ordered some Potato Semi flip flops.
Potato Semiconductor: http://www.potatosemi.com/
TI Logic Guide: http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf