Home > General, TEST > “LOWEST” DPLL Setting in Buffalo II DAC

“LOWEST” DPLL Setting in Buffalo II DAC

[Note: the reader is encouraged to read the previous posts in the subject, to understand the context of this post]

According to the information shared by the designers of the Sabre32 DAC, when you set the DPLL bandwidth setting to “LOWEST” in the Sabre32 DAC, you maximize the jitter rejection capability of the DAC while in its designed-for asynchronous operating mode, that is with the master clock generated by an on board clock, and with the on-board ASRC fully operational.

In theory, there is an optimal setting for the DPLL bandwidth. However, it is probably safe to assume that “LOWEST” in the Sabre32/Buffalo DAC is indeed “OPTIMAL” because it uses a top-end, ultra low noise oscillator.

After being able to identify the cause for unlocks with the DPLL setting at “LOW” (one notch above “LOWEST”) and having implemented a simple shielding solution that eliminated virtually all unlocks, I ran the tests again but this time setting the DPLL bandwidth at “LOWEST”. This is the ultimate test for the capabilities of the Sabre32 DAC as implemented in the Buffalo II and used in my own home environment. The USB interface is the Musiland 03 and the source is a Win 7 laptop with iTunes.

I let the Arduino/computer record the data for 27 hours. Here are the results:

Notice that when the DAC is powered-on, some time is needed for the clock to stabilize and thus the higher level of unlocks (this is normal behavior). Notice also the long stretch without any unlocks.

Comparing with my first set of measurements with DPLL setting at LOWEST, we see that with the casing/shielding fix, the unlocks have been greatly reduced. The graph below shows the original set of data collected during a 5-hour period. The number of unlocks per 10 minutes peaked at over 20. Now there are no data points above 10.


  1. I was totally surprised at the relative lack of unlocks and also at the lack of correlation between waking hours and sleep hours.
  2. We seem to have eliminated most of the airborne noise by using proper casing for the DAC. The number of unlocks have been greatly reduced, but at this DPLL bandwidth setting, they have not been totally eliminated.
  3. There doesn’t seem to be much noise sneaking in through the wiring as shown by the long stretch of no-unlocks during the waking/working hours.
  4. There are two “burst” of unlocks and they coincide in time (8-10 PM). I cannot relate this behavior to anything happening in the house. During the long stretch at night, the washing machine was on and it did not cause any unlocks.
  5. I have had the Buffalo II DAC for over two years, and have used different interfaces feeding the I2S inputs. All of this time I thought that the unlocks were caused by jitter in the interfaces, even with the currently used Musiland o3.  Not so!. If we look at the data, the long stretch (over 6 hrs) of playtime without a single unlock indicates that the the jitter in the I2S signals from the USB interface device are not large enough to cause unlocks even at this lowest setting of the DPLL bandwidth.
  6. The Musiland 03 seem better than I thought 🙂


  1. I can only think of more shielding. Perhaps on-board RFI shielding is required. Something similar to what Anedio has done.
  2. I2S isolation. We can use a device such as the NVE IL715 [link]. I already have a device and board and will test it when ready.


Normally, I set up the test and go off doing other things (like going work or sleeping). The test is done with the amp off. Last night for the first time I was able to enjoy several songs (after 10 PM -see data, only one unlock) with the setting at LOWEST. I didn’t even notice the single unlock I measured. I can’t say that I can clearly distinguish differences in sound, but as a diy-audio enthusiast, a successful tweak clearly adds to then enjoyment of music :-).

3/14/2012 Session

This time I used the computer while listening to music (like browsing the web). DPLL is again set at LOWEST. The unlocks recorded are unrelated to using the computer; they happened while I was NOT using the computer. I can’t figure out what caused the unlocks.

3/15/2012 Session

  • I collected data right from the time I powered the DAC for about 5hours. Notice the large amount of unlocks when the DAC is “cold” and the time it takes for DAC to stabilize (“warm up”) – I would say it takes about ONE hour.
  • I switched the power cable to a “shielded” cable, keeping the ferrite bead I had before and I also switched the USB cable with one that said “shielded” in the jacket, keeping the ferrite bead I had before. (The original USB cable was a USB-3 cable that probably is also shielded, but did not say so in the jacket). Doesn’t seem to make any differences
  • Still no correlation from the unlocks (after warm-up) with what was going on at home
  • The pattern of the unlocks indicates interference from somewhere rather than jitter in the USB interface.

Never too much shielding???

Added additional shielding to the DAC chip. To do this, I soldered two pin connectors to a small copper board and then plugged it in to the GND pins of the AVCC module as shown in the photos. In addition, I added some damping material to the oscillator in order to reduce vibrations.

The results: next post…

  1. January 14, 2015 at 23:24

    Hi, great articles, code you have in your blog. Really appreciate sharing this with the rest of us.
    I am using a Buffalo III fed from Amanero and controlled by an arduino mega2560 with your B11f code modified to use my T6369 lcd display.
    On the case of DPLL settings I have noticed that when oversampling is turned off even from cold and DPLL settings set to Lowest I have no unlocks no matter file resolution (44.1-192Khz). Turning oversampling on is a lost case for me as even after a couple of hours of opeation the unlocks are a very usual annoyance.
    How could that be explained?

    • BlgGear
      January 17, 2015 at 06:59

      Thanks. I don’t know why turning OS off would avoid the unlocks. However, with OS off, and with 44.1KHz material, you loose a lot of the top end information. It is possible the DPLL works better with lower sample rate (the OS Filter is before the DPLL according to the block diagram)

  2. September 14, 2016 at 16:09


  3. September 14, 2016 at 16:43

    Altieri Gilmore LLP Attorneys

  4. September 14, 2016 at 17:50

    Adonis Golden Ratio

  5. September 14, 2016 at 18:08

    best price comparison site

  6. September 14, 2016 at 19:15

    mortgage loan Roswell

  1. October 7, 2012 at 07:09

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )


Connecting to %s