Sabre32 DAC Unlocks: The Shielding Factor
I have effectively cut jitter in half!(?)
Shielding the DAC virtually eliminated the unlocks (with DPLL setting at “LOW”)
After shielding the DAC with a proper case, I ran the test for 24 hours straight, during which there was a lot of activity at home. Result: I got only two unlocks during the 24 hour period. I will repeat the test again to confirm these results, but this is very good news and has made this simple test tool incredibly useful for tracking down potential sources for noise and interference affecting the degree of jitter rejection capability of the Buffalo/Sabre32 DAC. I can now set the DPLL bandwidth to “LOW” and thus increasing jitter rejection 2X (see background section)
Just for comparisons, this is the data I got prior to providing proper shielding to the DAC (and with only 19 hours of measurements)
I was very surprised to see that shielding the DAC yields such improvement or that the DAC is susceptible to airborne noise (RFI/EMI) and interference to such an extent.
In any case, the results gives validity to board level shields as implemented by some manufacturers as can be seen below in their Anedio 2 DAC (photo from head-fi)
Other factors to consider: Perhaps the casing configuration I used separating the power and everything else from the Buffalo II board, also contributes to this improvement. Perhaps even affixing the AVCC power module under the board (thus being shield by the GND plane) is also a contributing factor.
The Sabre32 DAC has a variable DPLL bandwidth setting which allows adjusting the amount of jitter filtered (or rejected) from the input signal. The (minimum) bandwidth setting depends on the input format (spdif or I2S), the sample rate of the incoming signal and also whether or not the DAC is cold (as in starting up).
While the Sabre32 allows the adjusting of the DPLL bandwidth, there is a point at which the DPLL can no longer lock to the signal. It has been widely reported that for 44/1 Khz sample rate I2S, setting the bandwidth to “LOWEST” will result in unlocks. Users in Japan have reported that the “minimum” (no unlocks) setting for 44.1Khz is “MID-LOW” which is two notches above “LOWEST”. This is the setting that I have been able to achieve with my own setup.
The Sabre32 DAC has the following available settings for the DPLL bandwidth: LOWEST-> LOW-> MID-LOW-> MID-> MID-HIGH-> HIGH-> HIGHEST-> BEST. Each step represent a doubling the bandwidth value. Thus BEST has a bandwidth value that is 128x the value of LOWEST. Using the “BEST” setting will allow locking into the incoming signal independently of the aforementioned factors of sample rate, format and whether the DAC is cold or warmed up. Using LOWEST results in the maximum jitter rejection capability the DAC was designed for.
… the performance will get worse as to set the bandwidth higher and higher, since the jitter attenuation is reduced as you open up the DPLL as it were.
…If you choose higher bandwidth setting, the DPLL locks faster but lets more jitter through. Your tradeoff.
I suspect that most (if not all) implementations of the Sabre32 DAC ship with the DPLL setting set at “BEST” because you cannot afford to experience any unlocks on a shipping product. However, in a DIY environment, you can experiment with the different values for the DPLL bandwidth and see the effect.
Thus, if one could lower the DPLL setting from “MID-LOW” to “LOW“, then one could decrease the bandwidth by a factor of two and double the jitter rejection capability of the DAC.
Next: figure out what it takes to use “LOWEST”
Note: see the earlier posts for the full context of these results