DIYINHK Isolated XMOS USB Interface
DIYINHK has developed a new version of the XMOS-based USB to I2S Audio Interface. This version provides isolated I2S signal lines. Plus it uses superior oscillators.
You can read about the older version here [link]
The Isolator chip is the Silicon Labs 8661 Low Power 6-Channel Digital Isolator [link]. This is the newest device from Silicon Labs. It is based on RF coupling [link]. Apparently the Si-Labs isolators are the lowest cost ones [link]
Si86xx enhancements include:
- Schmitt-triggered inputs for higher input noise immunity
- Increased ESD protection
- High noise rejection linear regulators to ensure quiet bias voltage
- Lower power oscillators for greater operating efficiency and faster output buffers with tightened 50Ω source impedance for better matching
- Compared to competing digital isolators, Si86xx products provide near zero EMI emissions
- Industry’s highest data rate (150 Mbps) across the widest temperature range (-40 to 125 ºC) and low power operation of <1.6 mA per channel at 1 Mbps.
The “clean” side of the isolator requires a separate power supply which must be provided for proper functioning. You need to provide a 5-16V supply. This will be further regulated by a low noise regulator.
According to DIYINHK, this version uses NDK NZ2520SD Ultralow phase noise oscillators from Japan. There are 3 oscillators: the 48 MHz for the digital circuitry of the XMOS device, the 45.158MHz and 49.152 MHz for the audio frequencies.
NDK has some general information on their oscillators, including jitter data here: [link]. Below is the phase noise plot of the NDK oscillators. Note the phase noise curve of the “SD” models.
NDK’s NZ2520SD low-phase-noise crystal oscillator has phase noise characteristics superior to those of the general NZ2520SB model. The company’s high-accuracy crystal oscillator (OCXO) has even better phase noise characteristics near the reference frequency.
Here is the phase noise plot of the Xpresso oscillators used in the previous version
And here is the phase noise plot of the CCHD-957. Note the phase noise value of the CCHD-957 at 10 Hz (-97) vs the phase noise value of the NDK oscillator at 10 HZ (-113)
The Master Clock is available straight from the NDK oscillators or at the appropriate scaled-down frequency through the output pins.
Straight from the oscillators (45.158MHz and 49.152 MHz) through a U.FL socket:
Through the output pins (22.5792Mhz/24.576Mhz).
The “C7424Z” device is used as a clock divider to generate the 22.xx and 24.xx frequencies used by XMOS device and also used by the downstream device (the DAC). Seems the clock line to the XMOS device is also isolated in order to prevent any kind of noise leakage from the XMOS/USB side to the Clock/Clean side.
Note that there is no “re-clocking” of any of the I2S signals. However, Xout can be used to control an external re-clocking board for the I2S lines.
As we’ve seen, the “clock section” including the I2S signal lines is isolated from the “XMOS/USB section”. The master clock line generated by the local clocks that connects to the XMOS device is also isolated. The two sections are powered independently.
On the backside of the board, we can see that the ground planes are also separated between the “clean side” and the “dirty side”:
The XMOS side (or “dirty side”) is powered by USB by default. Just like in the earlier version, the USB power can be bypassed by removing the FB1 ferrite and external 5V power can be applied through the external power connectors.
For the advanced DIY’er, the XMOS device can be reprogrammed with different firmware. This can be accomplished through the CN6 connector (which is the JTAG interface for the XMOS chip):
The following device from XMOS, the xTAG-2 [link] can used to upload new firmware to the XMOS device (updating firmware through USB is not enabled in the default firmware). The xTAG-2 provides a high speed, low latency bridge between USB on the host and fast JTAG connection (up to 10Mbps) on the target.
JTAG enables the transfer of data into non-volatile device memory (uploading firmware).
There are 20 pins in this device because the device is also a debugger. The JTAG interface pins are specified in the hardware manual [link]