Building the $99 ES9018 DAC Board (Part I)

Previous post here: Board: [link]

GROUND PLANE MOD

Note: the current version of the board has a solid ground plane, so this mod only applies to early versions  (like mine) of the board. You can see the new version here: [link]

It is an industry best practice to have a continuous and mostly uninterrupted ground plane in any layout “no matter what”. This allows for uninterrupted ground current returns, following a lowest impedance path and also terminating (confining) the electric fields of power and signal lines. Now this doesn’t mean “completely solid”, but the aim is to have as continuous as possible. In a two-layer approach, this is harder, but according to industry documentation, a well designed 2-layer approach would approach 98% of the capability of a 4-layer PCB.

The return ground current likes to flow under or along the signal paths. That is, if you have electrons flowing in the signal paths on one direction, then there are electrons flowing in the opposite direction right under or along the signal lines. This is just the law of physics, otherwise you will be piling up electrons on one side of a conductor and this is impossible. (It is more complex than this, but this is the simplest explanation).

According to “Op Amp Applications Handbook” by Walt Jung, p. 640 (link),

Whenever there is a break in the ground plane beneath a conductor, the ground plane return current must by necessity flow around the break. As a result both the inductance and the vulnerability of the circuit to external fields are increased. This situation is diagrammed in figure 7-32 where conductors A and B must cross one another

This board has mostly a continuous ground plane except it is broken by the opamp power lines. If you follow the output of the DAC, there are 4 lines that connect DAC to opamps. The return ground current under the signal path would want to follow the signal path but it is interrupted by the power lines and thus it has to flow around. This is cause for added distortion (how much and whether audible or not? I don’t know).

In order to remedy this, I’ve installed bridges right under the signal path where it is interrupted by the power lines. In fact there are 5 such locations in the board.

The 5th location is this one. There is no “6th location” because in that location, the ground plane is uninterrupted.

I think, 24 gauge (cat-5 cable) wire is sufficient. Here is compared with an 18 gauge cable. Flattening the wire allows for easier soldering (it won’t roll around the board). Actually I will install a wider “strip”. See the text below.

Scrapping off the pads takes some patience and for me, a lighted magnifying lens 🙂

According to this document from TI [link]

One thing that many people forget about is for a current to flow out to a point, there MUST be a return path or else current will Not flow. Since there is a current flow, then the return current flow will find a way back to its’ source one way or another.

Return current density is highest directly under (or over) the signal trace it was sourced from. Even if a solid ground plane is used, the concentration of current flow will still be adjacent to the signal source trace.

Therefore, a wider bridge is better than a narrow bridge, but certainly a completely solid ground plane (which is desired) is not required to handle the return current.

Further thoughts

According to “Successful PC Grounding” the return current path has been characterize with relation to the signal frequency. At low frequencies (1KHz), the return current mostly flows across the shortest physical distance. At high frequencies (1MHz), the return current path is mainly under the signal path. This basically says that the return current follows the path of least inductance.

The following two diagrams shows the return current path for low and high frequency signals red/yellow/green showing the highest current concentration.

This means that at audio frequencies, a large portion of the ground return current will follow a path of shortest physical distance.

I’ve added another path for the signal ground return current to flow back to the DAC, one straight from the ground pins of the single ended output to the DAC chip, crossing the power lines.

Here are the photos with the installed ground current bridges:

I suspect this is the path of the return ground current. As there are no ground connections in any of the opamps, the signal return current is that which is coming back from the components downstream from the DAC. At audio frequencies, most of the return current would want to follow a path of shortest physical distance. Some will flow back under the signal lines.

It can be noted that even without the return current bridges, the return current flow with the original board is not that bad: the current just makes a long curve on its way to the DAC.

The new version of the board has a solid ground plane

CLOCK INSTALLATION

Tried to figure out what’s the best way to install a removable clock on this board. Ian had developed a clock carrier board, so I decided to use it. Here is what I have:

Installed a female pin header/socket connector to the carrier board

Used smaller headers that “standard”. These are metric 2 mm pitch headers. The typical ones are 0.1″ pitch. The pins are the ones used to connect the AVCC to the Buffalo DAC

Scraped the solder mask to expose the Vcc and GND planes. Since the connector is low profile, the clock can also be used in Ian’s FIFO reclocker board by installing the pins. Clock out and enable will be connected with wires to the respective pads.

The clock board connects to pins that are installed in the clock pads in the DAC board in the following manner. I bent the pins first, put them on the pin header and soldered them to the pads -an easy job.

The clock carrier board connected to the DAC board:

SAW (Surface Acoustic Wave) clocks

There has been some interest in using SAW clocks for the ES9018 DAC, and favorable results have been reported [link] even though these oscillators measure poorly as compared with the Crystek clocks typically used with the ES9018:

A 100mHz Epson SAW was compared to the 100mHz Crystek fitted as standard to the Twisted Pear BII… The outputs of each dac could be switched on the fly to feed the pair of I/V transformers. Of the 5 listeners, 3 clearly favored the SAW, and 2 (including myself) were undecided though one of us would choose the Crystek if forced to. The SAW, even to me, appears to have better resolution.
…

The Epson 100 MHz clock is available from Digikey for under $4 [link], datasheet [link]. Technical details [link]. Epson has some leading technology in SAW oscillators [link]

According the Epson, the SAW oscillators have advantage over traditional crystal oscillators. I’ve pulled this info from their documentation

Type	Circuit	Example	Jitter
SAW	Fundamental, high frequency oscillation and high drive	Epson XG-1000CA (106 Mhz)	Excellent. The noise floor is a low because of the high drive operation, and the high frequency is a steady fundamental oscillation.
Crystal (Fundamental)	Fundamental, high frequency oscillation and low drive		Excellent. Q value of the AT crystal unit is high and a fundamental oscillation though the noise floor goes up more than the SAW oscillator due to the lower drive level.
Crystal (3rd Overtone)	Overtone, high frequency oscillation, low drive and fundamental supression	Crystek CCHD-950 (100 MHz)	Good. The oscillation stability is inferior to two above-mentioned methods because the fundamental oscillation is suppressed and overtone is oscillated.

Note: 3.3v 100 MHz parts are not available from Digikey, so I linked 106 MHz parts for reference. It is not recommended to use parts in excess of 100 MHz

“Standard Oscillator”

Another good part are the FOX Xpresso oscillators. Available for under $4 for a 100 MHz part, 25 ppm frequency stability, 3.3V and in 7×5 mm size [link]

Jitter for a 100 MHz part can be calculated from the measurement plot provided in the datasheet (I have plotted the curve for the Crystek CCHD-80 which was standard equipment on the original Buffalo II DAC.

The phase jitter value 10Hz-1MHz for a 100Mhz part is approx a very respectable 2.7 psec. RMS.

ES9018 POWER CONSUMPTION [link]

Analog 3.3V supply

• AVCC-R (3.3V) = 32mA
• ACCC-L (3.3V) = 32mA

Buffalo II AVCC is 50 mA per side including the shunt current through the regulator [link]

Current consumption for AVCC also depends on the clock frequency and the actual voltage. The chip can operate all the way to 4 V (although many do not recommend doing so). According to a “Analog Power Supply Consumption” [link], the relation with voltage and frequency is as follows (I took the data from ESS and extrapolated it to 100 MHz and also beyond 3.8V):

Analog 1.2V supply

• AVDDL (1.2V)= 8mA
• AVDDR (1.2V)= 8mA

Digital 1.2V supply. This is the “core” of the DAC

• DVDD (1.2V) = 105mA

KlipschKid over at diyaudio [link] has done some measurements of the 1.2V supply (which combines both the analog and digital 1.2v supplies) with respect to clock frequency.

I’ve plotted his results (subtracting 5 mA used by the 7805 regulator)

There is also the current value for a 50 MHz SAW oscillator, at 110 mA [link] which is kind of on the high side but still ballpark value.

I had previously measured [link] the power consumption for the B-II 80 MHz DAC and found the current to be at 250 mA total. If we subtract the 100 mA for the AVCC and the 10 mA for the  clock, we end up with 140 mA for the 1.2V(+3.3V digital) supply. This matches well with the graph above.

If playing 192KHz sample rate vs 44.1KHz, the overall current consumption increases 30 mA.

Digital 3.3V supply

• DVCC_T (3.3V) = 5mA
• DVCC_B (3.3V)= 5mA

Oscillator supply

• VOSC (3.3V)= 10mA. Actually for the CCHD-957/950, the current consumption of the oscillator is 15 mA typical and 25 mA max

IMPLEMENTING THE 1.2V SUPPLY

There are three 1.2V supplies for the ES9018 chip, analog left, analog right and digital core. these are supplied by a single 1.2V regulator.

Here is some evidence that there is no need to feed the analog supplies separate from the digital supply (NOTE: most of my knowledge on this comes from the good people at diyaudio especially Russ of TPA who have shared a lot of information with us diy folks.):

I conversed with Dustin about this at length as well as experimented on my own. The 1.2V supplies that are on the analog side are actually just driving level shifter gates into the modulators from the core. It makes no difference if they are powered separately whatsoever. [link], [link]

and

The 1.2V supplies only do two things in the DAC, the first is that it drives the core of the chip. This is of course crucial. The second is it drives the gates of level shifters (a high impedance) into the quantizers.

It is important to understand what these level shifters do. They simply shift the bits from 1.2V core voltage to 3.3. They do not effect the analog reference voltage. In fact the reason it is imperative that the AVCC be an extremely low impedance is because the frequencies involved are extremely high. All the VDD supply has to do is maintain enough voltage to keep gates of the Qs saturated. The AVCC supply is crucial because it has to absorb and source current at very high frequency and with very low noise at the same time.

Now it is important to bypass the VDD pins well (as I have done) but these pins are not in any way tied to the analog reference voltage.

The key to good results is a clean very low impedance AVCC supply.

…[link]

The 1.2V regulator

The 1.2v supply powers the core of the DAC  and it is therefore a pretty important supply. The recommended regulator is the widely used and low noise ADP151-1.2 and can supply 200 mA maximum.

The operating current at 100 MHz clock frequency (160 mA) is already very close to the max that this regulator can provide. In addition, if higher sample rate material is used, then we are getting very near (or at) the max operating current.

I think a more capable regulator is a good idea. I like the LT1963A which can provide up to 1500 mA. (we audio diy types like overkill :-)). The adjustable version can be configured to provide to 1.21V and it is also the lowest noise configuration for the family.

Noise is 14 uV RMS (compared to the ADP151 at 9 uV RMS). Page 18 of the datasheet [link] says:

The LT1963A regulators have been designed to provide low output voltage noise over the 10Hz to 100kHz band-width while operating at full load. Output voltage noise is typically 40nV/√Hz over this frequency bandwidth for the LT1963A (adjustable version). For higher output voltages (generated by using a resistor divider), the output voltage noise will be gained up accordingly. This results in RMS noise over the 10Hz to 100kHz bandwidth of 14µVRMS for the LT1963A increasing to 38µVRMS for the LT1963A-3.3.

Compared to the LT1763 (used in Buffalo II) it is actually lower noise at the lower end of the frequency scale (<1KHz) and almost the same at the higher frequencies. At, say 100 Hz, the noise density of the LT1963A is 40 nV/SqrHz and for the LT1763 it is near 300 nV/SqrHz.

The LT1963a is also designed for Fast Transient Response. I’ve looked at many datasheets, the LT1963 seems the lowest noise of the “fast transient” LDOs. Fast transient is specifically designed for powering digital cores such as DSP, FPGA and in this case the digital core of the ES9018.

Modding the board and regulator

The challenge here is to install it in the board since the footprint is for the ADP151.

Comparing the pin assignment of the ADP151 and LT1963 we realize that they are kind of mirror image of each other.

For 1.21V operation, the ADJ pin in the LT1963 is tied to the OUT pin. SHDN is the EN(able) pin.

Flipping the LT1963 and bending the pins the other way should do the trick.

Scrape the solder mask to make the pads.

Checked the ground pads to determine the correct pin orientation. For 1.2v operation pins 1 and 2 are shorted. Pins 3 and 4 can also be shorted. Made pads for pins 5 (input) and 7 (GND). Pin 6 and 8 can be connected with wires.

The wire connects the enable pin to high (input voltage)

These are the bypass capacitors I used. The regulator output bypass is 100 uF with 30 mOhm ESR. According to the datasheet a minimum of 5 mOhm for a 100 uF capacitor is required for stability and reduced ringing. There is an ELNA 1000uF on the input side.

Works as specified: 1.21V. I used two alkaline batteries as input voltage and 10 ohm resistor as load (120 mA of current)

IMPLEMENTING THE 3.3V AVCC

The conventional wisdom is to use a shunt regulator for low noise and low impedance.

I think I will use the ultra low noise TSP7A47 series regulator from TI and add capacitors in parallel to the bypass capacitors for the AVCC supply lines to improve the transient response.

AudioLab uses such a configuration:

Here is a mockup with 5 mm capacitors:

I2S CONNECTIONS

Here is a good reference post from diyaudio [link]

We’re talking about basic high speed digital design, i.e. we want the logic 0/1 to arrive at the destination (where it matters) at the right levels and at the right time.

The uni-directional (transmitter –> receiver) signal is as simple as things can get and is what I2S runs on. You worry about reflection when the wire/trace is long and/or when the signal risetime is fast (e.g. a simple reset signal from a FPGA can have issues). To help alleviate that, series termination (located at the transmittter) is the simplest form. Your PCB stackup and trace width/separation should also be design to match the impedance characteristics (e.g. 50ohms usually for single-ended, USB is 85ohms differential).

Now how do you know if your circuit is well taken care of? You look at the signals with a scope (proper probing required). You want to ensure that the signal rise/fall edges are monotonic, under/overshoot is within spec and crosstalk from adjacent signals are acceptable. The first 2 parameters are achieved by proper high speed layout techniques (use termination, proper pcb traces, minimal via transitions, no routing over plane splits, etc). The last parameter is achieved by proper pcb layer stackup design and wise routing.

Do NOT EVER put caps on digital transmission lines. Series caps are typically for AC coupling (more commonly seen with PCIe than I2S). Parallel caps can snub terminations but the danger here is that they slow down the risetime of the signal and can lead to loss of timing margin (data setup/hold).

Series termination are used successfully for far more complex stuff, e.g. SPI at 50MHz, DDR2/3 at 500MHz. Typical values are 22R-33R. I have never seen 47R series termination resistors in any embedded design. I was just at Embedded Systems Conference West in San Jose. Saw plenty of reference designs, including I2S/digital audio stuff. Nope, no 47R there.

Look up Dr Howard Johnson’s books (the digital designer, not the hotel chain). Lots of good info.

For the typical hobbyist like the OP with a simple I2S circuit, I’d just put my chips as close together on the PCB as possible and call it a day. If you like to cable I2S from one board to another, then that is where you’ll run into issues. Most important point for cabling I2S is to ensure adequate ground returns for every signal (e.g. you use ribbon cable, put a GND wire next to every signal, use a 2-row connector with one row being all GND pins). Consider active buffering if your cabling is long.

Continue reading here: Part II: [link]