Jitter Specification: a Summary

Don’t you hate it when you are given a jitter number and you don’t k now if they are talking “period jitter” or “phase jitter”?  And even if the numbers are clearly specified as period jitter or phase jitter, you still don’t even know how they compare with each other?

Here I attempt to give a “good” rule-of-thumb to convert period jitter to phase jitter in order to facilitate the comparison of jitter numbers that are given out by the audio and electronics literature.

PHASE JITTER

Clock people often specify jitter numbers in “phase RMS jitter”

In a square wave, most of the energies are located at the carrier frequency.  However, some signal energies are “leaked-out” over a range of frequencies on both sides of the carrier.  Phase jitter is the amount of phase noise energy contained between two offset frequencies relative to the carrier (fc). Figure 6 is an unfiltered phase noise plot and the shaded areas represent the phase jitter between frequencies f1 and f2 (SiTime Corp. “Clock Jitter and Measurement”)

As an example, the table below shows the jitter specification of the Si570 clock from Silicon Labs:

Spectrum analyzers can automatically measure phase jitter and give a value between specified frequency ranges

Phase jitter specification is often given as values in a phase noise plot. Below is composite phase noise plot of different oscillators. The graph was generated from phase noise numbers given in the specifications. (Note: the plots for each oscillator are for a particular center frequency, usually specified in the datasheet. For example, the data for the Crystek 950 is for the 80 MHz clock. In order to do a true “apples to apples” comparison on phase noise, the same center frequency must be specified. But the combined plot below sort of give you some idea of their relative performance)

In order to find the phase jitter RMS value, one can use a “jitter calculator”, for example this one from Silicon labs [link]. I like the use the one from Jitter Time [link].

PERIOD JITTER

Whereas jitter for clocks is often specified in phase RMS values, logic people (FPGA, flip-flops) often specify jitter as “Peak-to-Peak Period Jitter”.

Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period (the frequency of the clock). (Xilinx datasheet).

SiTime recommends measuring 25 times a 10,000-sample test to determine  the peak-to-peak jitter values (and also the RMS (standard deviation) value). The image below shows a histogram captured by a Wavecrest SIA-4000C analyzer (SiTime Corp. “Clock Jitter and Measurement”):

It is important to note that the RMS value here (which is “Period Jitter RMS”) is  in most cases not the same as the Phase Jitter RMS value given in the specifications. Later we shall see the relationship between the two.

JDEC Standard

The JDEC standard specifies the minimum requirements to measure jitter in the time domain. In p.2 of the document, it specifies a minimum of 10,000 cycles to measure period jitter. Companies are free to use any number of cycles hopefully above the minimum recommended in the standard. For example SiTime uses  250,000 cycles; Xilinx, in this document gives an example of jitter measurement over almost 900K samples. Xilinx specifies “100,000 to 1,000,000” cycles.

As an example, the table below, an excerpt from the Xilinx Spartan 3 family datasheet, shows the jitter specification of the different clock outputs in period jitter peak-to-peak values.

Relation between RMS value and peak-to-peak value

To find the relation between RMS and peak-to-peak, we must  know the test methodology used in the measurement. In particular, it is important to know how many samples were used to measure the jitter value. The more samples you use in a measurement, the probability that a sample will move further in the extremes will increase and thus the peak to peak value increases. If the sample size is “sufficiently large”, then the distribution of the samples will be “Normal” or “Gaussian” and the RMS value remains the same regardless of how much larger is the sample size.

Thus the relation of RMS to Peak-to-Peak value depends on the number of cycles. For example in the plot above, the measurement device provided the RMS value (2.57 ps) and the peak-to-peak value (20.36 ps) and the number of cycles was 10,000. Given these values, the conversion is

peak-to-peak=7.9xRMS (sample size=10,000 cycles)

In this other example, we are given the values: RMS=1.8839 ps; pp=14.275 ps, number of cycles=10,000. Given these values, the conversion is

peak-to-peak=7.6xRMS (sample size=10,000 cycles)

In fact, the paper SiTime Corp. “Clock Jitter and Measurement” gives the relationship between sigma (RMS value) and peak-to-peak value in relation to sample size.

For our 10,000 cycle examples above, we can see that the sigma is +/- 3.719 or  7.438 which is very close to that obtained from the measurements.

(Notice that the values on this table are the same as the value on the BER table found in this jitter conversion tool: [link])

Thus for period jitter, using a factor of 7.5 to convert RMS to peak-ot-peak is a reasonable number to use, even though the number of samples used in the test is seldom given. We can assume that they had followed the JDEC standard.

RELATION BETWEEN PHASE JITTER RMS, PERIOD JITTER RMS AND PERIOD JITTER PEAK-TO-PEAK

It would be a good if we can convert phase jitter RMS to Period Jitter RMS and vice versa. This way we can compare apples to apples when determining the effect of each component (such as clock or FPGA) within a system.

According the this paper [link], the period jitter RMS is roughly equivalent to the “weighted phase noise” over its wide-band integration. The weighted phase noise is the phase noise multiplied by a weighting factor.

In practice, the wide-band integration is done from 10 Hz to half the carrier frequency and in the example given in the paper the difference between the value obtained by integrating the phase noise is roughly the same as that obtained by integrating the weighted phase noise. (2.6 vs 2.0, an overestimate of around 20% )

For our purpose, it is way more convenient to obtain the Phase Jitter RMS with a calculator and we can then assume (if integrated from 10 Hz to half the carrier frequency) that it is roughly 20% higher than the Period Jitter RMS

Thus:

Period Jitter RMS ~ 0.8 x Phase Jitter RMS (from 10 Hz to 1/2 the carrier frequency)

and

Period Jitter peak-to-peak ~ 7.5 x Period Jitter RMS

therefore

Period Jitter peak-to-peak ~ 7.5/0.8 Phase Jitter RMS

or

Period Jitter peak-to-peak ~ 10x Phase Jitter RMS (10Hz to 1/2 carrier freq)

Note: according to a Xilinx engineer specified that period jitter peak-to-peak =~ 15x phase jitter RMS [link]. This is true only if the peak-to-peak jitter value was obtained by running a very large sample, such as that the sigma is in the value of 12 (12/0.8=15). This corresponds to a sample size of one billion (see table above). In the absence of specific sample numbers, it is safe to assume that the sample size follows industry standards which is in the order of 10,000.

OTHER REFERENCES

1. “Converting between RMS and Peak-to-Peak Jitter at a Specified BER” from Maxim [link]
2. “Phase Jitter” from Corning Frequency Controls [link]
3. “Phase Noise and Jitter Concepts” [link]