It is a great time to be an audio diy’er. There is currently great availability of quality boards aiming at providing the greatest fidelity with incredible VALUE.
Here are some side by side photos of the two USB-I2S interfaces I own.
Worthy of mention is the upcoming next generation Wave IO board. Mr. Lorien posted a sneak peek at his next generation board [link]
From the look of the layout, this board has electrical isolation of the outputs and flip-flop reclocking after the isolator.
It has been discussed that one can use “asynchronous” reclocking with a high frequency clock, that is a clock frequency not a multiple of the source sample rate frequency. This method has been used in the past and good results have been reported. See for example reclocking the TDA1545 (Monica DAC) with an 80 MHz clock [link]
Many have planned (including myself) to use the on-board clock of the Buffalo DAC (and other Sabre32-based DACs) in order to achieve “ultra low jitter” results.
But, there are some problems with the ES9018 on-board sample rate converter when dealing with this kind of clocking.
Russ just reported the following:
Previous post here: Board: [link]
GROUND PLANE MOD
Note: the current version of the board has a solid ground plane, so this mod only applies to early versions (like mine) of the board. You can see the new version here: [link]
It is an industry best practice to have a continuous and mostly uninterrupted ground plane in any layout “no matter what”. This allows for uninterrupted ground current returns, following a lowest impedance path and also terminating (confining) the electric fields of power and signal lines. Now this doesn’t mean “completely solid”, but the aim is to have as continuous as possible. In a two-layer approach, this is harder, but according to industry documentation, a well designed 2-layer approach would approach 98% of the capability of a 4-layer PCB.
The return ground current likes to flow under or along the signal paths. That is, if you have electrons flowing in the signal paths on one direction, then there are electrons flowing in the opposite direction right under or along the signal lines. This is just the law of physics, otherwise you will be piling up electrons on one side of a conductor and this is impossible. (It is more complex than this, but this is the simplest explanation).
According to “Op Amp Applications Handbook” by Walt Jung, p. 640 (link),
Whenever there is a break in the ground plane beneath a conductor, the ground plane return current must by necessity flow around the break. As a result both the inductance and the vulnerability of the circuit to external fields are increased. This situation is diagrammed in figure 7-32 where conductors A and B must cross one another
This board has mostly a continuous ground plane except it is broken by the opamp power lines. If you follow the output of the DAC, there are 4 lines that connect DAC to opamps. The return ground current under the signal path would want to follow the signal path but it is interrupted by the power lines and thus it has to flow around. This is cause for added distortion (how much and whether audible or not? I don’t know).
In order to remedy this, I’ve installed bridges right under the signal path where it is interrupted by the power lines. In fact there are 5 such locations in the board.
The 5th location is this one. There is no “6th location” because in that location, the ground plane is uninterrupted.
I think, 24 gauge (cat-5 cable) wire is sufficient. Here is compared with an 18 gauge cable. Flattening the wire allows for easier soldering (it won’t roll around the board). Actually I will install a wider “strip”. See the text below.
Scrapping off the pads takes some patience and for me, a lighted magnifying lens 🙂
According to this document from TI [link]
One thing that many people forget about is for a current to flow out to a point, there MUST be a return path or else current will Not flow. Since there is a current flow, then the return current flow will find a way back to its’ source one way or another.
Return current density is highest directly under (or over) the signal trace it was sourced from. Even if a solid ground plane is used, the concentration of current flow will still be adjacent to the signal source trace.
Therefore, a wider bridge is better than a narrow bridge, but certainly a completely solid ground plane (which is desired) is not required to handle the return current.
According to “Successful PC Grounding” the return current path has been characterize with relation to the signal frequency. At low frequencies (1KHz), the return current mostly flows across the shortest physical distance. At high frequencies (1MHz), the return current path is mainly under the signal path. This basically says that the return current follows the path of least inductance.
The following two diagrams shows the return current path for low and high frequency signals red/yellow/green showing the highest current concentration.
This means that at audio frequencies, a large portion of the ground return current will follow a path of shortest physical distance.
I’ve added another path for the signal ground return current to flow back to the DAC, one straight from the ground pins of the single ended output to the DAC chip, crossing the power lines.
Here are the photos with the installed ground current bridges:
I suspect this is the path of the return ground current. As there are no ground connections in any of the opamps, the signal return current is that which is coming back from the components downstream from the DAC. At audio frequencies, most of the return current would want to follow a path of shortest physical distance. Some will flow back under the signal lines.
It can be noted that even without the return current bridges, the return current flow with the original board is not that bad: the current just makes a long curve on its way to the DAC.
The new version of the board has a solid ground plane
Tried to figure out what’s the best way to install a removable clock on this board. Ian had developed a clock carrier board, so I decided to use it. Here is what I have:
Installed a female pin header/socket connector to the carrier board
Used smaller headers that “standard”. These are metric 2 mm pitch headers. The typical ones are 0.1″ pitch. The pins are the ones used to connect the AVCC to the Buffalo DAC
Scraped the solder mask to expose the Vcc and GND planes. Since the connector is low profile, the clock can also be used in Ian’s FIFO reclocker board by installing the pins. Clock out and enable will be connected with wires to the respective pads.
The clock board connects to pins that are installed in the clock pads in the DAC board in the following manner. I bent the pins first, put them on the pin header and soldered them to the pads -an easy job.
The clock carrier board connected to the DAC board:
SAW (Surface Acoustic Wave) clocks
There has been some interest in using SAW clocks for the ES9018 DAC, and favorable results have been reported [link] even though these oscillators measure poorly as compared with the Crystek clocks typically used with the ES9018:
A 100mHz Epson SAW was compared to the 100mHz Crystek fitted as standard to the Twisted Pear BII… The outputs of each dac could be switched on the fly to feed the pair of I/V transformers. Of the 5 listeners, 3 clearly favored the SAW, and 2 (including myself) were undecided though one of us would choose the Crystek if forced to. The SAW, even to me, appears to have better resolution.
According the Epson, the SAW oscillators have advantage over traditional crystal oscillators. I’ve pulled this info from their documentation
|SAW||Fundamental, high frequency oscillation and high drive||Epson XG-1000CA (106 Mhz)||Excellent. The noise floor is a low because of the high drive operation, and the high frequency is a steady fundamental oscillation.|
|Crystal (Fundamental)||Fundamental, high frequency oscillation and low drive||Excellent. Q value of the AT crystal unit is high and a fundamental oscillation though the noise floor goes up more than the SAW oscillator due to the lower drive level.|
|Crystal (3rd Overtone)||Overtone, high frequency oscillation, low drive and fundamental supression||Crystek CCHD-950 (100 MHz)||Good. The oscillation stability is inferior to two above-mentioned methods because the fundamental oscillation is suppressed and overtone is oscillated.|
Note: 3.3v 100 MHz parts are not available from Digikey, so I linked 106 MHz parts for reference. It is not recommended to use parts in excess of 100 MHz
Another good part are the FOX Xpresso oscillators. Available for under $4 for a 100 MHz part, 25 ppm frequency stability, 3.3V and in 7×5 mm size [link]
Jitter for a 100 MHz part can be calculated from the measurement plot provided in the datasheet (I have plotted the curve for the Crystek CCHD-80 which was standard equipment on the original Buffalo II DAC.
The phase jitter value 10Hz-1MHz for a 100Mhz part is approx a very respectable 2.7 psec. RMS.
ES9018 POWER CONSUMPTION [link]
Analog 3.3V supply
- AVCC-R (3.3V) = 32mA
- ACCC-L (3.3V) = 32mA
Buffalo II AVCC is 50 mA per side including the shunt current through the regulator [link]
Current consumption for AVCC also depends on the clock frequency and the actual voltage. The chip can operate all the way to 4 V (although many do not recommend doing so). According to a “Analog Power Supply Consumption” [link], the relation with voltage and frequency is as follows (I took the data from ESS and extrapolated it to 100 MHz and also beyond 3.8V):
- AVDDL (1.2V)= 8mA
- AVDDR (1.2V)= 8mA
Digital 1.2V supply. This is the “core” of the DAC
- DVDD (1.2V) = 105mA
KlipschKid over at diyaudio [link] has done some measurements of the 1.2V supply (which combines both the analog and digital 1.2v supplies) with respect to clock frequency.
I’ve plotted his results (subtracting 5 mA used by the 7805 regulator)
There is also the current value for a 50 MHz SAW oscillator, at 110 mA [link] which is kind of on the high side but still ballpark value.
I had previously measured [link] the power consumption for the B-II 80 MHz DAC and found the current to be at 250 mA total. If we subtract the 100 mA for the AVCC and the 10 mA for the clock, we end up with 140 mA for the 1.2V(+3.3V digital) supply. This matches well with the graph above.
If playing 192KHz sample rate vs 44.1KHz, the overall current consumption increases 30 mA.
Digital 3.3V supply
- DVCC_T (3.3V) = 5mA
- DVCC_B (3.3V)= 5mA
- VOSC (3.3V)= 10mA. Actually for the CCHD-957/950, the current consumption of the oscillator is 15 mA typical and 25 mA max
IMPLEMENTING THE 1.2V SUPPLY
There are three 1.2V supplies for the ES9018 chip, analog left, analog right and digital core. these are supplied by a single 1.2V regulator.
Here is some evidence that there is no need to feed the analog supplies separate from the digital supply (NOTE: most of my knowledge on this comes from the good people at diyaudio especially Russ of TPA who have shared a lot of information with us diy folks.):
I conversed with Dustin about this at length as well as experimented on my own. The 1.2V supplies that are on the analog side are actually just driving level shifter gates into the modulators from the core. It makes no difference if they are powered separately whatsoever. [link], [link]
The 1.2V supplies only do two things in the DAC, the first is that it drives the core of the chip. This is of course crucial. The second is it drives the gates of level shifters (a high impedance) into the quantizers.
It is important to understand what these level shifters do. They simply shift the bits from 1.2V core voltage to 3.3. They do not effect the analog reference voltage. In fact the reason it is imperative that the AVCC be an extremely low impedance is because the frequencies involved are extremely high. All the VDD supply has to do is maintain enough voltage to keep gates of the Qs saturated. The AVCC supply is crucial because it has to absorb and source current at very high frequency and with very low noise at the same time.
Now it is important to bypass the VDD pins well (as I have done) but these pins are not in any way tied to the analog reference voltage.
The key to good results is a clean very low impedance AVCC supply.
The 1.2V regulator
The 1.2v supply powers the core of the DAC and it is therefore a pretty important supply. The recommended regulator is the widely used and low noise ADP151-1.2 and can supply 200 mA maximum.
The operating current at 100 MHz clock frequency (160 mA) is already very close to the max that this regulator can provide. In addition, if higher sample rate material is used, then we are getting very near (or at) the max operating current.
I think a more capable regulator is a good idea. I like the LT1963A which can provide up to 1500 mA. (we audio diy types like overkill :-)). The adjustable version can be configured to provide to 1.21V and it is also the lowest noise configuration for the family.
Noise is 14 uV RMS (compared to the ADP151 at 9 uV RMS). Page 18 of the datasheet [link] says:
The LT1963A regulators have been designed to provide low output voltage noise over the 10Hz to 100kHz band-width while operating at full load. Output voltage noise is typically 40nV/√Hz over this frequency bandwidth for the LT1963A (adjustable version). For higher output voltages (generated by using a resistor divider), the output voltage noise will be gained up accordingly. This results in RMS noise over the 10Hz to 100kHz bandwidth of 14µVRMS for the LT1963A increasing to 38µVRMS for the LT1963A-3.3.
Compared to the LT1763 (used in Buffalo II) it is actually lower noise at the lower end of the frequency scale (<1KHz) and almost the same at the higher frequencies. At, say 100 Hz, the noise density of the LT1963A is 40 nV/SqrHz and for the LT1763 it is near 300 nV/SqrHz.
The LT1963a is also designed for Fast Transient Response. I’ve looked at many datasheets, the LT1963 seems the lowest noise of the “fast transient” LDOs. Fast transient is specifically designed for powering digital cores such as DSP, FPGA and in this case the digital core of the ES9018.
Modding the board and regulator
The challenge here is to install it in the board since the footprint is for the ADP151.
Comparing the pin assignment of the ADP151 and LT1963 we realize that they are kind of mirror image of each other.
For 1.21V operation, the ADJ pin in the LT1963 is tied to the OUT pin. SHDN is the EN(able) pin.
Flipping the LT1963 and bending the pins the other way should do the trick.
Scrape the solder mask to make the pads.
Checked the ground pads to determine the correct pin orientation. For 1.2v operation pins 1 and 2 are shorted. Pins 3 and 4 can also be shorted. Made pads for pins 5 (input) and 7 (GND). Pin 6 and 8 can be connected with wires.
The wire connects the enable pin to high (input voltage)
These are the bypass capacitors I used. The regulator output bypass is 100 uF with 30 mOhm ESR. According to the datasheet a minimum of 5 mOhm for a 100 uF capacitor is required for stability and reduced ringing. There is an ELNA 1000uF on the input side.
Works as specified: 1.21V. I used two alkaline batteries as input voltage and 10 ohm resistor as load (120 mA of current)
IMPLEMENTING THE 3.3V AVCC
The conventional wisdom is to use a shunt regulator for low noise and low impedance.
I think I will use the ultra low noise TSP7A47 series regulator from TI and add capacitors in parallel to the bypass capacitors for the AVCC supply lines to improve the transient response.
AudioLab uses such a configuration:
Here is a mockup with 5 mm capacitors:
Here is a good reference post from diyaudio [link]
We’re talking about basic high speed digital design, i.e. we want the logic 0/1 to arrive at the destination (where it matters) at the right levels and at the right time.
The uni-directional (transmitter –> receiver) signal is as simple as things can get and is what I2S runs on. You worry about reflection when the wire/trace is long and/or when the signal risetime is fast (e.g. a simple reset signal from a FPGA can have issues). To help alleviate that, series termination (located at the transmittter) is the simplest form. Your PCB stackup and trace width/separation should also be design to match the impedance characteristics (e.g. 50ohms usually for single-ended, USB is 85ohms differential).
Now how do you know if your circuit is well taken care of? You look at the signals with a scope (proper probing required). You want to ensure that the signal rise/fall edges are monotonic, under/overshoot is within spec and crosstalk from adjacent signals are acceptable. The first 2 parameters are achieved by proper high speed layout techniques (use termination, proper pcb traces, minimal via transitions, no routing over plane splits, etc). The last parameter is achieved by proper pcb layer stackup design and wise routing.
Do NOT EVER put caps on digital transmission lines. Series caps are typically for AC coupling (more commonly seen with PCIe than I2S). Parallel caps can snub terminations but the danger here is that they slow down the risetime of the signal and can lead to loss of timing margin (data setup/hold).
Series termination are used successfully for far more complex stuff, e.g. SPI at 50MHz, DDR2/3 at 500MHz. Typical values are 22R-33R. I have never seen 47R series termination resistors in any embedded design. I was just at Embedded Systems Conference West in San Jose. Saw plenty of reference designs, including I2S/digital audio stuff. Nope, no 47R there.
Look up Dr Howard Johnson’s books (the digital designer, not the hotel chain). Lots of good info.
For the typical hobbyist like the OP with a simple I2S circuit, I’d just put my chips as close together on the PCB as possible and call it a day. If you like to cable I2S from one board to another, then that is where you’ll run into issues. Most important point for cabling I2S is to ensure adequate ground returns for every signal (e.g. you use ribbon cable, put a GND wire next to every signal, use a 2-row connector with one row being all GND pins). Consider active buffering if your cabling is long.
Continue reading here: Part II: [link]
(1/28/13) Important Update: See comments section regarding reclocking with the DACs 100 MHz clock.
Even though the Amanero USB interface supports 352/384K sampe rates, if this high sample rate bitclock is reclocked with the original clock signal, the output is completely silent The DAC cannot see a signal to lock on. Here is the reason why:
Here is the truth table of a flip flop: the output (Q) reflects the input (D) on the rising edge of the clock (CLK) signal.
Here is a diagram illustrating the re-clocking of two signals: a 175.4 KHz sample rate signal and a 352.8 KHz sample rate signal. Keep in mind that at 352K sample rate, the frequency of the bit clock is the same as the frequency of the 22.5792 MHz on-board clock. (352.8K x 64).
Shown in red is the clock signal taken straight from the clock and fed to the flip-flop. In gray are the input signals coming from the CPLD and fed to the flip-flop. Since there is a propagation delay in the CPLD, they are shown with a delay in relation with the native clock signal. In green is the output from the flip-flop.
If we follow the truth table above, we can see that at 176.6K, the output can still follow the input but with the edges coinciding with the edges of the original clock signal. But with the 352K signal, we see that at the rising edge of the original clock signal, the input is always at the same value, hence the flat output.
At 352K, the Buffalo DAC correctly reports “No Lock”. Indeed, there is no signal to lock to.
Thus if using reclocking with the original clock signal, you will loose the ability to play 352k/384K, unless Amanero releases a new board with clocks with frequencies 2X the current values, or you manually bypass the reclocking flip-flop.
Rather than reclocking with the “source clock”, one can reclock with the “destination clock”. Russ has experimented with reclocking the I2S lines with the Buffalo 100 MHz clock (see comments below) with good results. Reclocking with the destination clock (the clock of the Buffalo DAC) would require reclocking all 3 I2S signal lines to ensure bit-perfectness.
“Destination clock” only applies to DACs that normally operate in asynchronous mode, generating their own clocks. I think only the ESS DACs would operate in this manner. Most other DACs require a master clock as required input.
The circuit, with Potato flip-flops would look something like this.
Still striving for unlock-free behavior, I implemented what Mr. Abraxalito recommended:
Be careful with ultra-fast CMOS logic – it does require extremely good decoupling. Inside CMOS devices the transistors crowbar the supplies (quite literally) every clock transition. I discovered this with 74AC chips many years ago – even there I was using a multilayer PCB. I suspect the Potato chips are considerably faster! Get the smallest package size you can solder, decouple with 0603s and use a ferrite bead on the positive supply to reduce the bounce on the GND. Even with these precautions you’ll get some jitter from the bounce on the positive supply. Good luck! [link]
After the mods:
Basically I added a ferrite to Vcc and a capacitor to GND. Effectively, including with the previous bypass capacitor, it is a CLC filter which is symmetric from either side of the supply line (meaning it should filter noise coming into the flip flop and noise coming out of the flip flop through the power line). I also paired the bit clock line with a ground wire to provide some shielding. Pretty standard and common sense tweaks.
Unfortunately I messed my my clean and professional looking implementation :-). If I were to do it again, I would put those components under the board.
Based on feedback from readers, I’ve replaced the “magic red cap” :-)) with a much smaller ceramic cap
Seems very positive: I did the first interval for the unlock test, from midnight to 8:00 AM and there were Zero unlocks. It “survived” the “morning hiccup” where at the start of the day, electrical activity would cause one or more unlocks… We will see what happens in the afternoon.
Unlocks after: (8 hrs play time)
after 20 hours, the results are really good. Have never gotten this kind of performance in the past: ZERO unlocks (except, of course for the warm up time). Here is the plot showing the full 20 hours of play time. Well, there is really nothing to show 🙂
This turned out a very effective mod, even with much less than ideal components. If done correctly (proper PCB with ground plane, proper bypass, compact layout, etc), the results would be even better (and finally beyond my “measurements” – not really, I just use higher sample rate material). Anyone wants to develop a small PCB?
SAMPLE RATE TEST
Used the Windows control panel (to generate a test tone) and high-res music files to test the following sample frequencies. The DAC (with HifiDuino software) validated the sample rate being received.
- 44.1 KHz (also tested with music file this sample rate)
- 48 KHz
- 88.2 KHz
- 96 KHz (also tested with hi-res music file of this sample rate)
- 176.4 KHz
- 192 KHz (also tested with hi-res music file of this sample rate)
I wasn’t able to test 352.8 KHz files on the Amanero. Not sure if it is the mod or the Amanero board. Previously I did not test high-res files on the Amanero board and, in addition, the control panel does not say that 352.8 KHz and 384 KHz sample rates are supported as shown below (there is no check-box)
This test also confirms that the CPLD in the Amanero board indeed toggles the enable lines of the oscillators depending on the input sample rates to allow only one oscillator operating at any one time. This makes the MOD possible as the flip-flop only has one clock signal input. Had the clocks been operating at the same time, then only one frequency family could be supported. Playing a song of the other sample rate family would have required manually switching the clock signal.
RESULTS OF UNLOCK TEST
For reference, here are all the tests plots I’ve done in the past. The time dimension of the plot correlates to the actual time of day. Although during the midnight hours there are practically no unlocks, during the morning hours the unlocks increase and sometimes they are worse than what is shown in the graph.
The firs plot corresponds to the Amanero board as delivered from the factory (click for larger size).
The following plot corresponds to the Amanero board with large input capacitors to the regulators.
This plot corresponds to the Amanero board with large input and output caps for the regulators.
Here is the plot adding the bit clock re-clocking mod.
I think there is some improvements. In all cases, the unlocks in the morning hours correspond to the start of electrical activities around the house.
I continue the measurement and did it until 6:00 PM. In the past, I did not continued the test after the morning hours because the unlocks seems to happen all the time, and thus I stopped. However, the afternoon plot looks very clean except for a burst of unlocks around 9:00 AM which also coincide with other members of the family getting up and starting another round of electrical activity. Seems once the DPLL of the DAC is disturbed, it takes some time for it to stabilize. In any case, the plot does look cleaner overall than what I have observed in the past. I think there is marked improvements.
The “burst” behavior is very strange. Even though it correlates to electrical activity, at other times of the day there is even more electrical activity but no unlocks.
Let me repeat what I said already that this has been a most satisfying modding experience…
- Education: I got to learn about flip flops.
- Cost: the only new part I purchased was the Potato Semi flip flop for $3. But even if I had to buy everything, the entire cost would still be < $10
- Looks: this mod came out looking like a professional job 🙂
- Recycle: The small resistors for tapping the clock lines came from old VCR.
Some shielding of the wires may be advisable…
Got inspired by the synchronous reclocking of the bitclock mod that was shared in the Amanero thread over at diyaudio. [link]. Very low cost mod that promises very high results. We are talking a few bucks to potentially drastically reduce jitter.
Here is the Potato Semi flip flop. Here I describe why I chose the Potato flip-flop [link].
Just got them in the mail (in a small hand-written envelope – unlike those large companies what would have sent FedEx in a huge box :-)). I purchased two just in case. It is a Dual Flip Flop (only one is needed), but they don’t come in single configurations:
I need power (3.3V), ground and bit clock from the Amanero board:
The 3.3V power supply from the Amanero board can provide up to 50 mA:
The Potato flip flop only consumes a miniscule amount:
Potato Semi flip flop on a SOIC to DIP adapter board. Unfortunately the only pin I could line up with the Amanero board is the bit clock pin to the input of the flip flop.
Made the necessary connections on the backside of the board: power, ground and the Q and Q-bar outputs for the flip flop. Yeah, no ground plane, but better connections would require a custom PCB.
Mounted on the Amanero board, nice fit.
Used 0.1 uF film capacitor bypass close to the 3.3 V power pin (could be closer, but the Vcc and Gnd pins in the chip are diagonally opposite to each other):
The Clock signal for the flip flop can be tapped from R8 or R9. This is the native, low jitter master clock straight from on-board oscillators. One of the concerns is how to switch between the two clocks as both are needed. Fortunately it was reported that both clock lines can be tied together and connected to the clock input of the flip flop.
Apparently only one clock is active at any one time. By looking at the circuit diagram, the clocks have enable lines that are controlled by the CPLD and thus the CPLD can decide which clock should be enabled and which clock disabled. This is a very nice feature as it allows the re-clocking chip to use both frequencies and thus support both sample rate families: 44.1K and 48K.
I think I’ll make the connections to the two clocks like this:
Here is tapping the clock signals: (yes it is an antenna, but it is the shortest distance). The resistors are the smallest I could find in my recycle bin. Any small value should work I used 220 ohm resistors. The board uses 47 ohm resistors on the clock and data lines.
I have both the Q and Q-bar pins available. Right now it is connected to Q. Late I will use the Q-bar output and see what is the effect.
The entire module will be put in a metal case. That is why I had to reposition the OSCON capacitors. This will provide additional protection against EMI.
I think the box needs a logo or something to look “professional” 🙂
Works right away! and sounds pretty good.
I did a quick test on the different sample rates, 44.1, 48, 88.2, 96, 176,4 and 192 and they all work. I will later do my customary unlock measurement…
I must say, this has been a most satisfying mod.
Here is a much better done mod by bigpandahk [link]:
Here is a board being developed by Acko [link]
Here is an implementation of synchronous reclocking the I2S signal in the Amanero board reported on diyaudio:
After improvement of getting MCLK from XO instead of using standard PIN 6, I tried reclocking the BCK with same MCLK and the improvement is very positive. Right now I tied PIN43/44 on CPLD together, fed MCLK to reclocker and DAC with 2K resistor. The reclocker is 74AUC1G74 D-type flip-flop at 2.5V (power pull from 3.3V with 330ohm in series). Left side is PCM5102 DAC
The basic idea is to:
- Feed the oscillator clock signal directly to the DAC
- Use the oscillator clock signal to drive a flip flop which reclocks the Bit Clock
This reclocking scheme can be done with any USB-I2S where you can tap a low jitter clock signal. Typically these are the ones that derive the clocks from oscillators rather than internally by the FPGA. A good candidate is Lorien’s XMOS-based WAVE IO
The goal is to reduce jitter in the I2S signals, including the master clock by leveraging the fact that the jitter added by a flip flop is much less than the jitter added by a CPLD or FPGA.
Even thought the on-board oscillators are low jitter, the signals coming out of the CPLD have a minimum amount of jitter in the order of 100 psec peak to peak. If we take the master clock straight from the oscillator rather than from the CPLD, we don’t have the added jitter by the CPLD. If we also use this clock signal straight from the oscillator and re clock the bit clock, then this new bit clock will also be of lower jitter than the original bit clock coming out of the CPLD.
HOW DOES IT WORK?
“When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse.”
Here is a logic table for a typical flip-flop (this one taken from Potato Semi 74G74 datasheet)
Basically, the flip-flop re-aligns the edges of the bit clock to the edges of the master clock. From the above table, rows 4 and 5, D (data input) is reflected at Q (output) on the rising edge of the CLK (clock). Thus if we use the clock signal directly from the oscillator (low jitter), and feed the bit clock from the CPLD to the D input of the flip flop, it will be “reclocked” resulting in a lower jitter signal at Q (output)
RECLOCK LR CLOCK AND DATA?
Data is read in reference to the bit clock. As long as the minimum timing requirements are met (set up and hold times), a value of 1 will be read as 1 and a value of zero will be read as zero. It is probably safe to assume that systems are designed with sufficient timing margin that even with a more jittery bit clock, there are no digital errors. Therefore, there is no need to reclock the LR clock and the DATA
WHAT ABOUT TIMING?
There are some timing considerations we need to think about with regard to this manner of reclocking. The master clock coming out of the CPLD is synchronized with the other I2S signals (Bit clock, LR clock and Data). In comparison to the clock signal at the oscillator output (oscillator clock), these signals have a certain amount of propagation delay just for the fact that they have gone through the CPLD device. I am not exactly sure how much is the propagation on the output signals, but based on the CPLD datasheet, it may be in the order of 10 (or 10s) nano-seconds.
When the bit clock is reclocked with the oscillator clock, the new reclocked bit clock will be further delayed because it would have likely missed the rising edge of the oscillator clock (the signals out of the CPLD are delayed by the propagation delay) and would have to wait for the next rising edge of the clock signal.
How much is the bit clock delayed?
As discussed, the flip flop aligns the new bit clock to the rising edge of the oscillator clock. The oscillator clock is ahead (timing wise) of the master clock to which the bit clock is synchronized. The bit clock would have likely missed the rising edge of the oscillator clock and needs to wait for the next rising edge of the oscillator clock. The resulting new bit clock is thus delayed ONE PERIOD time of the oscillator clock. (It could be half a clock period depending how the signals are synchronized to the master clock: rising or falling clock edge)
One period for a 22.5792 MHz clock is 44 nsec. The bit clock for 44.1 KHz material is 354 nsec. The potential maximum delay of the new bit clock is a small percentage of the width of the bit clock which in this case is 44/354=12%. There should be no problems as also reported working by the poster above.
However, for higher sample frequencies, the delay becomes a larger percentage of the bit clock width. If we look at 172K material, the bit clock period is 88 nsec and the delay in the new reclocked bit clock is 50%. Perhaps this will still work. Increasing the sample rate further, say 352K sample rate, the delay is the same as the width of the bit clock. This will result in completely missing the first bit of the data signal.
- The Experimenter above uses 74AUC1G74 D-type flip-flop (operates at 1.8v)
- A better fit with 3.3V operation is the SN74AUP1G74
- Also recommended in the forums with even wider operating voltage: 74VHC74
- This flip flop is used in Ian’s FIFO Clock board (3.3v operation): 74AUP1G79
- Potato Semiconductor 74 Series Logic: PO74G74A. Extremely fast and very low propagation delay.
Some would argue that because the Potato Semi device is the fastest device, the added jitter is smallest. This would make sense. The technology used by Potato Semi in their devices are based on noise reduction which helps reduce jitter.
WHO IS POTATO SEMICONDUCTOR?
Based on the funky name, company log0 and the bare design of their website, Potato Semi seems a company of dubious reputation. However this is a company that have invented some cool technology. Here is the invention if you are interested in reading patents [link].
According to the press:
Potato Semiconductor, a leading IC design company focusing on the high speed CMOS I/O field, has successfully applied its innovative technology to 74 series logic ICs. Using advanced technology, this new generation of 74 series logic ICs features high performance, high frequency and low noise. The running speed can be 5 to 7 times faster than existing 74 series ICs which continues the prevailing trend in electronics design — high speed and high performance.
But the strongest vote of confidence comes form Ian’s FIFO reclocker. He has experimented with Potato Semi chips and has selected it for his latest clock board [link].
The chip can be purchased direct through eBay for $3. Not cheap in comparison with standard logic chips which cost in the order of $0.50. But for a few bucks you can (theoretically) drastically reduce the output jitter of the Amanero board (or other interface with similar design)
INTERFACING TO BUFFALO DAC
The synchronous reclocking approach described here seems ideal for interfacing with the Sabre DACs for the following two reasons:
- The oscillator frequency of Amanero (22.5792 MHz and 24.576 MHz) is below what the Buffalo DAC considers “normal” which is higher than 40 MHz. So the best way is to operate the DAC in its normal asynchronous mode, taking advantage of the DAC’s local oscillator
- The DAC locks to the bit clock, therefore it is desirable to generate a low jitter bit clock with this method of using a flip flop driven by a low jitter oscillator clock
- Reduce jitter to the absolute minimum possible with the board
- Easy to do, low cost
- May not work for higher sample frequencies
This would be a very nice and interesting (and very cheap) mod. Definitely worth trying it out. I’ve already ordered some Potato Semi flip flops.
Potato Semiconductor: http://www.potatosemi.com/
TI Logic Guide: http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf
Don’t you hate it when you are given a jitter number and you don’t k now if they are talking “period jitter” or “phase jitter”? And even if the numbers are clearly specified as period jitter or phase jitter, you still don’t even know how they compare with each other?
Here I attempt to give a “good” rule-of-thumb to convert period jitter to phase jitter in order to facilitate the comparison of jitter numbers that are given out by the audio and electronics literature.
Clock people often specify jitter numbers in “phase RMS jitter”
In a square wave, most of the energies are located at the carrier frequency. However, some signal energies are “leaked-out” over a range of frequencies on both sides of the carrier. Phase jitter is the amount of phase noise energy contained between two offset frequencies relative to the carrier (fc). Figure 6 is an unfiltered phase noise plot and the shaded areas represent the phase jitter between frequencies f1 and f2 (SiTime Corp. “Clock Jitter and Measurement”)
As an example, the table below shows the jitter specification of the Si570 clock from Silicon Labs:
Spectrum analyzers can automatically measure phase jitter and give a value between specified frequency ranges
Phase jitter specification is often given as values in a phase noise plot. Below is composite phase noise plot of different oscillators. The graph was generated from phase noise numbers given in the specifications. (Note: the plots for each oscillator are for a particular center frequency, usually specified in the datasheet. For example, the data for the Crystek 950 is for the 80 MHz clock. In order to do a true “apples to apples” comparison on phase noise, the same center frequency must be specified. But the combined plot below sort of give you some idea of their relative performance)
Whereas jitter for clocks is often specified in phase RMS values, logic people (FPGA, flip-flops) often specify jitter as “Peak-to-Peak Period Jitter”.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period (the frequency of the clock). (Xilinx datasheet).
SiTime recommends measuring 25 times a 10,000-sample test to determine the peak-to-peak jitter values (and also the RMS (standard deviation) value). The image below shows a histogram captured by a Wavecrest SIA-4000C analyzer (SiTime Corp. “Clock Jitter and Measurement”):
It is important to note that the RMS value here (which is “Period Jitter RMS”) is in most cases not the same as the Phase Jitter RMS value given in the specifications. Later we shall see the relationship between the two.
The JDEC standard specifies the minimum requirements to measure jitter in the time domain. In p.2 of the document, it specifies a minimum of 10,000 cycles to measure period jitter. Companies are free to use any number of cycles hopefully above the minimum recommended in the standard. For example SiTime uses 250,000 cycles; Xilinx, in this document gives an example of jitter measurement over almost 900K samples. Xilinx specifies “100,000 to 1,000,000” cycles.
As an example, the table below, an excerpt from the Xilinx Spartan 3 family datasheet, shows the jitter specification of the different clock outputs in period jitter peak-to-peak values.
Relation between RMS value and peak-to-peak value
To find the relation between RMS and peak-to-peak, we must know the test methodology used in the measurement. In particular, it is important to know how many samples were used to measure the jitter value. The more samples you use in a measurement, the probability that a sample will move further in the extremes will increase and thus the peak to peak value increases. If the sample size is “sufficiently large”, then the distribution of the samples will be “Normal” or “Gaussian” and the RMS value remains the same regardless of how much larger is the sample size.
Thus the relation of RMS to Peak-to-Peak value depends on the number of cycles. For example in the plot above, the measurement device provided the RMS value (2.57 ps) and the peak-to-peak value (20.36 ps) and the number of cycles was 10,000. Given these values, the conversion is
peak-to-peak=7.9xRMS (sample size=10,000 cycles)
In this other example, we are given the values: RMS=1.8839 ps; pp=14.275 ps, number of cycles=10,000. Given these values, the conversion is
peak-to-peak=7.6xRMS (sample size=10,000 cycles)
In fact, the paper SiTime Corp. “Clock Jitter and Measurement” gives the relationship between sigma (RMS value) and peak-to-peak value in relation to sample size.
For our 10,000 cycle examples above, we can see that the sigma is +/- 3.719 or 7.438 which is very close to that obtained from the measurements.
(Notice that the values on this table are the same as the value on the BER table found in this jitter conversion tool: [link])
Thus for period jitter, using a factor of 7.5 to convert RMS to peak-ot-peak is a reasonable number to use, even though the number of samples used in the test is seldom given. We can assume that they had followed the JDEC standard.
RELATION BETWEEN PHASE JITTER RMS, PERIOD JITTER RMS AND PERIOD JITTER PEAK-TO-PEAK
It would be a good if we can convert phase jitter RMS to Period Jitter RMS and vice versa. This way we can compare apples to apples when determining the effect of each component (such as clock or FPGA) within a system.
According the this paper [link], the period jitter RMS is roughly equivalent to the “weighted phase noise” over its wide-band integration. The weighted phase noise is the phase noise multiplied by a weighting factor.
In practice, the wide-band integration is done from 10 Hz to half the carrier frequency and in the example given in the paper the difference between the value obtained by integrating the phase noise is roughly the same as that obtained by integrating the weighted phase noise. (2.6 vs 2.0, an overestimate of around 20% )
For our purpose, it is way more convenient to obtain the Phase Jitter RMS with a calculator and we can then assume (if integrated from 10 Hz to half the carrier frequency) that it is roughly 20% higher than the Period Jitter RMS
Period Jitter RMS ~ 0.8 x Phase Jitter RMS (from 10 Hz to 1/2 the carrier frequency)
Period Jitter peak-to-peak ~ 7.5 x Period Jitter RMS
Period Jitter peak-to-peak ~ 7.5/0.8 Phase Jitter RMS
Period Jitter peak-to-peak ~ 10x Phase Jitter RMS (10Hz to 1/2 carrier freq)
Note: according to a Xilinx engineer specified that period jitter peak-to-peak =~ 15x phase jitter RMS [link]. This is true only if the peak-to-peak jitter value was obtained by running a very large sample, such as that the sigma is in the value of 12 (12/0.8=15). This corresponds to a sample size of one billion (see table above). In the absence of specific sample numbers, it is safe to assume that the sample size follows industry standards which is in the order of 10,000.