Home > DIY HiFi, General > Inside the Silicon Labs Si570 Programmable XO

Inside the Silicon Labs Si570 Programmable XO

October 17, 2012 Leave a comment Go to comments

Found an interesting photo on the internals of the Si570 clock.

Above images taken from here: [link]

When the manufacturer first introduced the device, it provided the following jitter phase plot [link]

Taking the data from the plot we have:

Offset f – Phase Noise

  • 10 -65
  • 100 -98
  • 1000 -106
  • 10000 -116
  • 100000 -122
  • 1000000 -135
  • 10000000 -146

Phase noise data with Si570 data from datasheet, the Crystek 957 and the Crystek 950 from their respective data sheet:

Frequency Si570 (datasheet)
CCHD-957 (49.152 MHz) CCHD-950 (80 MHz)
10 Hz N/A -98 dB -70 dB
100 Hz -112 dB -129 dB -102 dB
1000 Hz -122 dB -153 dB -135 dB
10000 Hz -132 dB -162 dB -160 dB
100000 Hz -137 dB -168 dB -166 dB
1000000 Hz -144 dB -168 dB -166 dB

If we calculate the RMS jitter we obtain the following:

  • Si570 (Original factory jitter values) With center frequency of 100 MHz: 2.91 psec RMS
  • Si570 (Original factory jitter values) With center frequency of 80 MHz: 3.64 psec RMS
  • For Si570 (Jitter values from current data sheet, assuming -82 for 10 Hz) With center frequency of 90.3168 MHz:  0.52 psec RMS
  • For CCHD-950 -80MHz: 1.90 psec RMS

Even comparing the original factory spec values for the Si570 vs the CCHD-950, the Si570 is not that much higher in terms of jitter 1.9 psec vs 3.6 psec.

As with other manufacturers, the jitter performance is often improved with newer versions. But even with better (datasheet) jitter specifications, Ian’s listening impression indicate that the Si570 is still not up to the CCHD-950 performance [post 913]:

Although the Silicon Labs official document mentioned that the Si570 is not quite sensitive to the PSU noise, I found it’s not true, at least for this application. The close-in phase noise performance of Si570 is not as good as CCHD950, 957. So, to compete with them, the Si570 needs better, lower noise PSU. Both 1/f noise of the PSU and the XO crystal itself contribute to the close-in phase noise. After I bypassed the on board low noise LDO and made the Si570 directly powered by a LiFeP04 3.4V battery cell, ESS9018 sounds better with more details and more liquid.


Ian is currently perfecting his implementation of the Si570-based clocking board, including permanent  battery operation and full electrical isolation from the FIFO board. Looks like a real winner

(Source: post )

(Source: post 951) )

(Source: post 980 )


There is also a interest list for this board (I think 50 is the minimum): [link]


Not of the Si570 but a “common” oscillator from a scrap board. The lid is glued so tight and the ceramic case would first break

Notice the crystal with an electrode above and another electrode below.

  1. October 18, 2012 at 00:47

    Great review! I likes those analysis as found useful for my RF designs.

    Just want to point you one new solution based on Si5351 programable clock generator which can be driven with some high quality oscillators (for example some of Connor-Winfield models with < 1ppm) if you need variable frequency output or some non-standard values.

    Also, here are large offer of various oscillators: http://www.digikey.ca/product-search/en/crystals-and-oscillators/oscillators/852334

    On other hand, if you looking for extremely low phase noise, consider some best in class Wenzel's oscillators!

    • BlogGeanDo
      October 18, 2012 at 05:53

      mikikg, thanks for the comment. You guys were the pioneers in using the si570 for diy projects. I will check out the si5351.

  2. qusp
    October 18, 2012 at 01:08

    I think Ian has been very careful with his comments and comparisons to other clocks, as ashamedly he may open himself up for ridicule, gotta love the forum…. he doesnt say he preferred one over the other if you read carefully, he simply says it needs a very low noise power supply to compete. Thats my reading of it anyway.

  3. qusp
    October 18, 2012 at 01:17

    mikikg: close in phase noise is the most important spec for us and we need multiple Fs ability, otherwise there are other options like Wenzel, NDK and the Crystek in the comparison. low phase noise and the ability to do the higher audio clock speeds like 90.3168MHz or 98.304MHz are the reason for pursuing this design. for audio frequencies we are already using the lowest noise in the digikey catalogue, we have to search elsewhere and add the $$$ to do better.

    I also had looked at their catalogue early when we were talking about this part and wondered about combining the Si5351 with a really high quality SC cut fundamental crystal, but I would think incredibly tight PCB layout (no problem, Ian knows what hes doing there) and probably higher end measurement gear than we have available (heck, higher than most companies have available) would be needed to tune the design.

    now that we have the great result from this board, I wonder if we could pursue this…. see we need group buying power to get these things off the ground each time, or the cost becomes prohibitive.

    • qusp
      October 18, 2012 at 01:27

      not Si5351, phase jitter is a bit too high @ 3.5ps RMS, I still think the idea has some merit, I wonder if there are higher end parts available elsewhere of the same nature.

      • BlogGeanDo
        October 18, 2012 at 06:07

        Yeah, used in the FIFO clock board, is high, but can be used in FPGA designs…

  4. October 18, 2012 at 11:40

    Yes, mentioned jitter for Si5351 is specified when it is used as oscillator with attached quartz. If you connect some external oscillator it will have jitter which oscillator have with one note that phase nose will be 20dB lower if you divide fundamental frequency by one decade or 6dB lower if you divide by octave. More info here: http://hanssummers.com/ddssi570.html

    • BlogGeanDo
      October 18, 2012 at 16:00

      Thanks, good read.
      I have also read other sites learned a lot from the detailed analysis and measurement.

      One think I noticed though (as compared to the audio people) is that there is not much discussion on the the need for clean power (low noise regulator, bypass, layout). Seems much lower noise regulators can be used than the ones recommended in the different kits. Can you comment?

      • October 18, 2012 at 23:35

        That mostly depends on constructor’s choice and price for good low-noise regulators which can be up 10 times higher. I use TPS7A4901 in some radio construction.

        Also, there is one major reason why not using low-noise devices (exm. radio receivers for less then 30MHz) is in that radio noise in ether/air (left from big-bang) is much higher than noise figure of modern components. For higher frequency radio devices, noise figure becomes critical. For example, those who mess with radio-astronomy takes extreme steps like cooling devices with helium to get as much as low thermal noise of its receivers🙂

        On other side, audio technics demands components with much lower noise figure in start.

      • BlogGeanDo
        October 19, 2012 at 04:07

        Very interesting. Didn’t know Big Bang noise was a concern for you guys. TPS7A4901 is a good choice.

  5. October 18, 2012 at 11:46

    Also, Silicon Labs produce clock jitter cleaner ICs which are mostly for very high frequency (>800MHz) and if you additionally divide that source you can get very low jitter.

  6. qusp
    October 19, 2012 at 15:04

    we are not only talking about lower noise LDOs, but discrete regulators with orders of magnitude lower noise and over a wider bandwidth

    interesting idea re dividing it down, thanks for that I guess I hadnt considered that a series circuit for division could lower the noise further. I wonder if we could do the same with the Si570, it appears much happier at higher speeds, we could double or quadruple the Fs and divide down externally with a much lower noise part.

    glt, see this is the cool thing about this part and this type of design in general, we can play the numbers, change FS at will to suit an agenda with no price attached.

    • BlogGeanDo
      October 19, 2012 at 15:46

      Here is a good paper: http://www.silabs.com/Support%20Documents/TechnicalDocs/Clock-Division_WP.pdf
      Although the phase noise curve is indeed lower when the clock is divided, the integrated phase jitter actually increases slightly. This is because when calculating the RMS phase jitter, you need to enter the clock frequency into the equation.

      I think in theory the phase jitter value should remain the same. The paper argues that the higher increase in the lower frequencies is due to equipment noise floor and “aliasing”.

      Therefore, I think, the simpler the better… (no clock division)

      • qusp
        October 19, 2012 at 16:42

        thanks for the link, i’ll check that out on the ipad tomorrow on the beach =) as you say the increase at lower Frequencies is due to noise floor, but probably also due to less PSRR in both the power supply and the internal PLL at lower frequencies.

  7. qusp
    October 19, 2012 at 15:08

    I do wonder though if any of these techniques for lowering overall noise really helps us down at 10-100Hz where we need it the most

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