Home > USB AUDIO > Amanero Long Term Measurement (II)

Amanero Long Term Measurement (II)

October 13, 2012 Leave a comment Go to comments

Previously, I had tested the Amanero USB board with respect to unlocks [link]. Aiming at cleaning up some of the unlocks, I added output caps to the regulators. Now the regulators have both input and output caps.

I attached the capacitors to the small SMD output caps of the regulators.

CAUTION: this is probably not the best way to install the capacitors. I put a slight pressure on the cap to straighten it and it immediately pulled the smd cap off the solder pads. Luckily I was able to solder the smd cap back to the solder pads. If you install it this way, exercise care in handling the board. It is safer to solder the caps either vertically or tilting inwards.

Here are the results (click for larger image)

For reference, here are the results for input cap mod only:

Seems fairly the same; maybe a bit cleaner, but with one test, I think it is within the statistical variance of the measuremets.

Based on the design, this board promises very low jitter.  The local regulators are already very low noise and have been used in other good implementations. Good bypass is used throughout. LC filters are also used for powering the on-board clocks. You can read more here [link].

However, there are more unlocks in this board as compared with the Musiland device. I had already implemented a series of mods in the Buffalo II DAC where together with the mods on the Musiland I was able to have zero unlocks even during a 24 hour period, thus I am confident that the unlocks observed here are primarily from the Amanero board.

We can conclude therefore that both the Amanero and Musiland devices are low jitter devices, with the Amanero having at least a design edge for lower jitter but the Musiland seems to have an edge with respect to blocking external disturbances  such as noise sneaking through the power line and EMI. Even with the use of DC-DC switching converters, the Musiland seems more capable of providing a more stable environment resulting in less or no unlocks. In fact, after 9:00 AM, the numbers of unlocks for the Amanero board got worse (I suppose people are awake and there are more electrical activity in the house and neighborhood).

Both of the devices are designed to be powered through USB, the only difference is that the Musiland is a finished product and has a case and the Amanero is an OEM product and comes in the form of a bare board. Installed with the BII DAC, the Amanero resides inside a case; the Musiland resides inside its case which is inside the DAC case providig additional shielding. I don’t know if this is a factor but I will test this out at a later date. Perhaps also, the LC networks used to filter the switching regulators in the Musiland also provide additional resistance from external disturbances. The only other difference is the USB cable. The Musiland uses a generic USB3 cable and the Amanero uses a generic USB2 cable. Based on my observation, it seems the Amanero board requires additional power conditioning in order to achieve its potential.

For now, the Musiland is working better in my system.

  1. Javier
    October 13, 2012 at 20:25

    Have you considered removing the ADP-150 and feeding the board from an external PS?
    A friend tried it with a lowly 317 and reported very good results with his B-III.

    • BlogGeanDo
      October 13, 2012 at 23:32

      Not considered having an external power supply. However, if using a 317, then I think it is better to cut the trace supplying the ADP-150 and attach the external supply there.

  2. Javier
    October 14, 2012 at 07:12

    He specifically ordered his Amanero without the ADP-150 so he didn’t have to cut anything, just use the power pins at the back of the card. The 317 was just for quick testing, I think his intention was to use a Salas BiB as the permanent PS.

  3. t28
    October 15, 2012 at 18:26

    Things to consider:
    Lowest DPLL setting offer the best jitter rejection but as a consequence need a high long term clock stability.
    So don’t care of the phase noise of your source, the sabre is designed to overcome it, but be carefull with the clock stability.
    To feed the ess clock : very low phase noise.
    To feed the ess data clock (I2S bit clock) at lowest DPLL setting : very high long term stability like a good tcxo, ocxo, gps clock etc ….

    • BlogGeanDo
      October 15, 2012 at 20:53

      Thanks for your comment. In the tests, the unlocks with DPLL=LOWEST happens when you turn on the DAC from cold. After a while, the system is in steady state and one can achieve lock for long periods of time. Seems the unlocks happen not so much because of jitter in the signal but because of some disturbance (power line, etc)

  4. t28
    October 15, 2012 at 22:30

    “Power line disturbance” could be view as a sort of “slow noise” or 1/f noise too.
    As a test, you could try to flow hot air and cold hair on the BII or on your source to simulate long temp instability. It correlate perfectly with the “warm up” of the DAC from cold, it is the warm up of the cchd.
    As the dac need very low jitter for it own clock the cchd is better, but need good thermally controlled environment to be as stable as possible. Use a case to prevent big air flow&temp variation.
    For the source, a tcxo is the best choice.
    Power glitches contribute to the unlocks, but are not the only or root cause of them.
    Remember the crap sony spdif which never lock ? The problem is not jitter, but fast frequency shift/instability (which could be view as very very … very big and very very … very slow jitter).

    • BlogGeanDo
      October 16, 2012 at 06:02

      I think being in a case is a good idea. Perhaps this is the problem with the Amanero. TCXO is also a good idea, but not easily implementable in the devices I use. I will try a case for the Amanero…

  5. t28
    October 15, 2012 at 22:33

    “the crap” -> “some crappy”
    And all my excuses for my crappy English writing ability too …

  6. t28
    October 15, 2012 at 22:43

    And at last, with synchronous clock, no unlock which fit the picture too.
    If I remember correctly, Lowest DPLL setting operate with a control loop on a window of more than a minute (a lot more if my memory is good) which is more a style exercise than a real DA conversion performance improvement.

    • BlogGeanDo
      October 16, 2012 at 06:03

      If I may ask that you repeat your comment in with different words, I could not quite understand…

  7. t28
    October 16, 2012 at 21:33

    I wanted to say two things in my last comment:
    First, that with the ESS running with a main clock in sync with the data the data clock (synchronous mode), there is no unlock which is coherent with the long term stability/slow frequency shift theory.
    Secondly, that “lowest” DPLL setting operate with a control loop on a window of more than a minute (a lot more if my memory is good). For two “not in sync” clock and not by either mean long term stable clock (temperature controlled, oven controlled etc ..), this is an impossible mission to maintain the DPLL locked. And such a long control loop does nothing more on the quality of the digital to analog conversion, it is a “just for fun” setting, a “not to be used in real life” design validation/test setting.
    To get a solid DPLL lock at “lowest” setting, without sync clock, we need two long term very stable clock. But we know that on the ESS side phase noise matter more than long term stability.
    So the trade of is to use a higher setting witch will not degrade the Digital To Analog conversion but will give us a lower jitter result with a very low phase noise clock on the ESS side, and without unlock.

    • BlogGeanDo
      October 18, 2012 at 06:04

      Hello, thanks for your comment. Yes I agree with the synch mode. I will do that mod later… Regarding your second comment, I am able to get long term lock with DPLL set at lowest. Although I would probably agree with you that it is a “just for fun” setting, does it not remove the most jitter from the source?

  8. t28
    October 18, 2012 at 21:01

    At this loop duration, what we try to remove is no longer in the jitter domain but in the pure frequency shift domain and thus the “jitter eliminator” is not more efficient than a more reasonable setting, and as a bad bonus could lost lock.

    • BlogGeanDo
      October 19, 2012 at 00:20

      That is very interesting. Have not heard this explanation before. Can you recommend some links for further reading? Thanks.

  9. peufeu
    November 28, 2013 at 15:59

    Amanero feeds their clocks from the high noise PLD digital supply, so expected jitter/stability clock performance should be extremely poor.

    Adding noise by making a LC resonator using low-ESR OSCON caps with very long leads ain’t gonna help either. Those can also interact with the ferrite beads.

    Remember, a clock integrates power supply noise, turning voltage variation into frequency drift (some mfg list about a few ppm/volt).

    If the lowest setting on the ESS really has a bandwidth of a minute, you’d need ppm stability on I2S relative to local clock, not going to happen here.

    Also, the clock runs through the CPLD (add lots of noise) and through a connector with an extremely bad pinout for highspeed signals (ie, one ground pin shared with all other signals).

    All this doesn’t really matter as ES9018 is designed not to care. I don’t think that lowest bandwidth would be that useful anyway… only if I2S clock is PLL-synthetized from the DAC’s MCLK, in this case no problem with drift.

    Of course the cable with only 1 ground wire will radiate EMI like an antenna, that’s another problem.!…

    • BlgGear
      December 5, 2013 at 21:09

      Thanks for your comments. This is just trial and error and “measuring” its effect on the number of unlocks experienced by the DPLL in the DAC. It is just for diy fun. Certainly not for production. In any case, there doesn’t seem to be any adverse effect on perceived sound or the number of unlocks in the DAC.

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