Home > USB AUDIO > Another USB Interface for DIY

Another USB Interface for DIY

The company is called “Amanero Technologies” located in Pisa, Italy.

I am excited about this device because, well, it is cheap!.  Technology is always changing. For the audio hobbyist, there is no such thing as the “ultimate device” or “last upgrade”. Therefore buying cheap but well designed products is the best approach because soon enough you will replace it with something better. As the subtitle of this blog says, “Lot of Value, Little Money” 🙂

The design is similar to other USB to I2S interfaces such as HiFace, XMOS, ExaDevices, etc, but it is priced substantially lower without sacrificing any of the essential desirable features (and also without adding extra features). For example, it does not use any kind of signal isolators as they may only benefit certain noisy environments but always introduce jitter. I like the minimalist, low power, low noise and low jitter approach.

Data Sheet: [link]


  • Clean, very minimalistic design with no other feature than an I2S output and ready to be “plugged” into any DAC.
  • The local regulators are the now-popular ultra low noise ADP-150 and ADP-151 from Analog Devices.
  • The clock is taken from the two external local oscillators (and not generated by the FPGA) therefore keeping added jitter to the absolute minimum.
  • The external oscillators are powered by the ADP-151 regulators through an LC filter which further decreases power noise (not an exotic implementation, but good practice).
  • Supports up to 384 kHz and 352.8 kHz sample rates.
  • Supports DSD


  • Schematic for the USB interface (the Atmel chip): [link]
  • Schematic for the data clocker (the Xilinx chip): [link]
  • This is important for us diyers that can’t leave any design alone!

POWER [post 235], [post 238]

  • Self powered (USB VBUS). USB power goes through a π filter (CLC) before the local regulator. The second regulator (another ultra-low noise ADP device) takes its input from the first LDO. This results in even cleaner power to the CPLD, the data clocking device
  • In the output connector you have 3.3V from the LDO. For example you can use this pin to know when the cable is plugged.
  • If you don’t like the USB VBUS supply, you can remove the LDO and power the module directly from the 3.3V pin present in the output connector.
  • Power consumption is about 600 mW at maximum speed


  • Supports MAC OS, Linux and Windows


  • Single: US$97
  • 60+ units: US$49


USB Interface

The USB interface is an Atmel microprocessor (SAM3u1C). The choice of using a general purpose microprocessor as the usb interface makes this device different from all other interfaces which implement a specialized usb interface chip. I don’t know the reason, but perhaps this makes it much easier for upgrading the firmware of the microprocessor itself and also for updating the firmware of the Xilinx CPLD.

On a side note, the SAM3U microprocessor will also be used in the upcoming Arduino DUE

Data Clocking

The data clocking device is a Xilinx CPLD (XC264A). A CPLD is like an FPGA but lower complexity and lower power. Another guess: the designers choose the smallest device necessary just to do the I2S data and DSD clocking. No extra features like clocking a SPDIF stream.


Two low jitter clocks for deriving the master clock for the different sample rates

(Manufacturer’s data from post 78 at diyaudio)

-78dBc @10 Hz,
-115dBc @100Hz
-140dBc @1KHz
-150dBc @10KHz
-155dBc @100KHz
-156dBc @1MHz

Using a jitter calculator we get the following value:

Not bad. The crystek CCHD-950 80MHz originally used in the BII measured at 2.286 psec [link]

Pin description [post 238]

  • DSDOE: = 1 when a DSD stream is incoming.
  • MUTE: has been assigned to PIN 11 and is asserted to 1 when a sample rate change is incoming or when there is a stream format change DSD / I2S. You can use this pin to avoid noise when the dsd is detected.
  • Pin 6 is the Master Clock MCLK 22,5792Mhz or 24.576Mhz. (I think this is pin 5 FSCLK)
  • TWC.D is an I2C bus, I m preparing a ConfigTool that let’s the user configure Events in the module. For example you can assign I2C address and values to put in the I2C bus when the volume is changing or when a sample rate is changing.

There are a couple of fuzzy videos on youtube where you can get a glimpse at the driver user interface.


The Audiophilleo USB interface chip is also implemented in a general purpose microprocessor. According to 6moons,

(The Audiophilleo uses) an ARM9 microprocessor… The processing power is considerable and allows the Audiophilleo to provide advanced dithered digital attenuation, ramped muting, balance and polarity reversal on the fly. New firmware containing the code for all these functions can be downloaded in a few moments which in turn enables easy field upgrades. The resulting processed data are passed to the output stage through miniature galvanic isolators that are much faster than the usual optical types. A TDK Lambda regenerative power supply separates the rails and grounds of the two subsystems. So now we’ve got clean power and data neither of which is contaminated by dirty power or clocks.

… The “non-minimalist” design approach.


On paper (since I don’t have one yet :-)), this device seems like a winner; and considering the price, it should be at the top of the list. For the next level of improvements, you will have to look at something like Ian’s FIFO device. The only “unknown” at this point is how well has the USB h/w and s/w been implemented.


Readers know that I have been a long time fan of Musiland Devices. They are very affordable, have good drivers, and are fairly easy to mod. For the diyer, this device addresses the two things I wished Musiland had improve, namely lower noise regulators and clocks from external oscillators (rather than generated in the FPGA).  Feature-wise though, the Musiland devices still pack a lot of things for the money: more interfaces, built-in DAC, built-in headphone Amp, user-interface with lost of controls, etc. For an all-in-one USB solution, the Musiland devices are still on the top of my list.

You can join the discussion at diyaudio.

  1. August 29, 2012 at 11:19

    Looks like a winner to me, especially given the price. Is the Windows driver a ‘pukka’ one they’ve written themselves?

    • BlogGeanDo
      August 29, 2012 at 14:46

      Hi Richard,

      No idea about the driver. The endpoints can be configured as bulk or isochronous, maybe just a modified buld driver?

  2. Anonymous
    August 29, 2012 at 16:30

    If you’re interested check the GB over at Diyaudio. If we can get enough numbers the price is even more attractive!


    • BlogGeanDo
      August 30, 2012 at 18:26

      Thanks. However, I already purchased one and is already in the mail. I’ll upgrade when they develop version II :-). The group price is one crazy price. Hope this is a trend…

  3. ldm
    August 30, 2012 at 11:39

    Since it doesn’t specifically say, is this an async implementation?

    • BlogGeanDo
      August 30, 2012 at 16:47

      Reading the documentation of the Atmel parts, it seems to allow for defining the device as either isochronous or bulk; isochronous can be synchronous or asynchronous. So it could be either of the 3. Maybe it is using bulk? The musiland supports bulk and support 352K transfer rates. See here: https://hifiduino.wordpress.com/2011/02/05/bulk-transfer-mode-in-musiland-monitor-devices/.
      It could also be asynchronous like the EXA devices

  4. Anonymous
    August 30, 2012 at 23:28

    Other than spending as much as the board itself, will it make sense to replace the standard clocks with Crystek’s 957 for sync mode or would it be overkill?

    • BlogGeanDo
      August 31, 2012 at 01:07

      Likely the added jitter by the Xilinx chip is much higher than that of the external clocks. So I don’t think you will benefit from changing the clocks. The numbers provided by the manufacturer shows that the clocks already have good jitter numbers. But this is diy and one cannot leave the design alone 🙂

  5. Jeremy aka 'qusp'
    September 3, 2012 at 09:56

    so have you got yours yet? given the clocks are generated externally not by PLL, the jitter should only be added on the bck, wck, sdata lines yeah? i’ll probably be running it through fifo anyway and setting up 2 of the new TP OTTOs to allow bypassing the fifo for dsd content.

    • BlogGeanDo
      September 3, 2012 at 15:55

      Hello qusp,

      Yes, it is “in the mail”.
      If you look at the schematics, you can see that the output of the oscillators are connected to the CPLD and the master clock comes out of the CPLD, so all the signals have the added jitter of the CPLD which is in the order of 10ps RMS.
      I don’t think you can feed the clock directly to the DAC and at the same time have the other signals come from the DPLD because there is some delay going through the CPLD logic.
      PS: I just sent in my FIFO for firmware update…

  1. August 29, 2012 at 16:52
  2. September 18, 2012 at 16:07
  3. October 13, 2012 at 19:39
  4. November 19, 2012 at 21:57

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