Home > General > More “Jitter Measurement”

More “Jitter Measurement”

Below is a plot of Buffalo II with the DPLL bandwidth setting at “LOW” – one notch above “LOWEST”. Source is Musiland 03US/PC/Win7/iTunes.

Data is collected for 11 hours of continuous play looping the same song. Notice the long absence of unlocks during the early hours. Could it be due to noise in the electrical grid?

I am already using a power conditioner such as this:

Suspecting noise on the wires, I added a ferrite bead to the bitclock wire and reran the test from 11:00 PM to 8: AM. Results: no improvement. The graph below shows the new results overlayed on the original test. (Click for larger image)

Here is an explanation for loosing lock in a PLL from Atlera [link]

Jitter on PLL input clock is out of specification 

Excessive jitter on the input clock can cause the PLL to lose lock. For PLL input jitter specification.

Since the PLL acts as a low-pass filter, you can use it to filter input jitter as well. The programmable bandwidth feature allows you to control the low-pass response characteristics. To filter higher frequency jitter, use a low bandwidth setting. To track jitter, use a high bandwidth setting.

HIFIDUINO: Since we suspect jitter in the input, this is possible a cause for the loss of lock. However, by looking at the graphs, we see the unlocks showing up as glitches, and depending on the time of day. Thus, not very likely that it is due to excessive jitter at least at the setting used in the DPLL bandwidth

Simultaneous switching noise (SSN)

Excessive switching noise on the clock inputs of the PLL could cause the PLL to lose lock. Switching noise on the inputs is a form of deterministic jitter that is subject to the input jitter specification shown in the device family data sheet.

HIFIDUINO: Possible as the Musiland is powered by the laptop/USB

Power supply noise

Excessive noise on the VCCA plane can cause high output jitter and possible loss of lock. VCCA is subject to the same requirements (+/- 5%) as the other device power supplies. Again, you can use the PLL bandwidth setting to suppress some of the output jitter. Since VCCA powers the voltage controlled oscillator (VCO), noise on this supply could cause the VCO output frequency to fluctuate and cause jitter. A low bandwidth causes the loop to respond slower to the noise being injected by the VCO. In turn, it cannot adjust for this noise and counteract it. A high bandwidth, on the other hand, allows the loop to respond quickly to the noise and compensate for it.

HIFIDUINO: The Musiland 03 is powered by USB power. This is a likely cause for loss of lock

Input clock stops/glitches or there is a sudden phase change

A glitch or stopping of the input clock to the PLL could cause the PLL to lose lock. The PLL operates by using a feedback loop to track a reference clock. If the reference clock stops, the PLL no longer has a signal to track. If there is a sudden, drastic phase change of the input clock, the PLL may not be able to react quickly enough to maintain lock.

HIFIDUINO: “Drastic phase change of the clock”. I would guess that this is not happening, thus not a cause for the loss of lock

PLL is reset

Asserting the areset or pllena ports of the PLL causes it to lose lock. These ports reset all the PLL counters and reset the VCO to its nominal value.

HIFIDUINO: There is a register value to cause a “reset” as a “relock”, we we don’t use this setting for the test. Thus not a cause for the loss of lock

An attempt has been made to reconfigure the PLL

Once the scanwrite port is asserted, the PLL scan chain is uploaded to the actual counters. The PLL could lose lock during or after PLL reconfiguration if the M counter, N counter, or phase shift settings have changed during the reconfiguration process.

HIFIDUINO: We see this happening if we change the DPLL bandwidth setting. During test, the setting is not changed. Thus is is not a cause of the unlocks

Input clock frequency goes outside the lock range as reported in the Quartus II PLL Summary Report file

The input clock frequency must stay within the minimum and maximum lock frequency.

HIFIDUINO: The frequency of the bit clock stays pretty much the same. Not a likely cause for loosing lock


Based on the above analysis, it seems we should focus on cleaning up the power. My first attempt by inserting a ferrite bead did not lead to any improvements….

  1. Russ White
    March 3, 2012 at 02:03

    You aren’t measuring jitter in any way at all. You are simply measuring the frequency of unlock events, which can be and usually are due to factors completely unrelated.🙂 Still it is interesting. There is no replacement for measuring analog side bands to detect actual jitter. Oh that we all had the gear to do so… but alas…


    • BlogGeanDo
      March 3, 2012 at 05:43

      Hi Russ, thanks for stopping by. I know it is NOT jitter measurement, that is why I put it in quotes, One thing is for sure: the lower the bandwidth, the lower the amount of jitter that can pass through. The results show that the unlocks are not really caused by the device’s “inherent jitter”, but caused by something that causes perturbations on the bit clock.

      Can you suggest what might those external causes be?

      If one can tweak the devices and show improved unlocks, then at least that is worthwhile mod.

      In any case, given a choice I’d rather buy all the kits you will ever develop than an AP machine to measure jitter🙂

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