Home > Arduino, Code, TEST > Poor Man’s Jitter Measurement

Poor Man’s Jitter Measurement

February 26, 2012 Leave a comment Go to comments


It is well known that by setting the DPLL bandwidth in the Sabre32 DAC to its lowest level, results in the DAC being “overly” susceptible to incoming jitter. This is manifested by the DAC loosing lock on the signal. We can use this “property” of the DAC to determine a relative value of incoming jitter.


In order to measure the number of unlocks, I connected the outputs of the lock LED in the Buffalo II DAC to an Arduino. The Arduino detects the unlocks and logs that event with a time stamp.

The lock LED is replaced by a resistor (I used 5 Kohm) the then the two leads across the resistor are connected to Pin2 and GND in Arduino. The lock signal is a voltage applied to an LED. An unlock pulls that voltage to ground. This can be detected by generating an interrupt in Arduino.

I put tape on the pins that I did not use because I didn’t want to mistakenly connect a wrong pin (say a 5V pin) to the DAC and risk potential damage.

The data is logged to the Arduino serial monitor, which can be copied to a spreadsheet to generate graphs.


Below is the result of my first measurement. The Buffalo II DAC DPLL bandwidth is set at “lowest” and is connected to a Musiland 03US through its I2S input.

Each data point represents the number of unlocks in a 10 minute period. Notice that in the first 10 minutes after I turned on the DAC, there are many more unlocks due to the fact that the DAC goes through a “warm-up” period to stabilize its clock (this is a well observed behavior). The data also shows that it takes about 10 minutes for the DAC to stabilize.


Code to detect unlocks in BII DAC.
 The lock LED is replaced by a resistor the then the two leads
 across the resistor are connected to Pin2 and GND in Arduino
 By detecting the unlocks and recording it we can measure how
 many unlocks occurr during a specific amount of time.
 The lock signal is a voltage applied to an LED. An unlock pulls
 that voltage to ground. This can be detected by generating an
 interrupt in Arduino.

#define INTERVAL 10             // Arbitrary time interval in minutes

static boolean unlock=false;    // Flag
int total=0;                    // Total unlocks
int totalInterval=0;            // Total unlocks every time interval

unsigned long minutes=0;        // Minute count 0 to 59
unsigned long totalMinutes=0;   // Total minute count 0 to ...
unsigned long hours=0;          // Hours count 0 to ...
unsigned long lastInterval=0;   // Time in minutes of last interval

void gotUnlock()                // Interrupt handler
  unlock=true;                  // Interrupt indicates got an unlock

void printTime(){               // Prints hours:minutes as xx:xx

void keepTime(){                // Keeps track of elapsed time
    if(minutes==60){            // For every 60 minutes...
      minutes=0;                // Reset the minutes and...
      hours++;                  // Increase the hours

void printData(){
  Serial.print(" ");
  Serial.print(" ");

void setup() {
  pinMode(2, INPUT);            // Set pin 2 for input
  digitalWrite(2, HIGH);        // Turn-on pull-up resistor
  attachInterrupt(0, gotUnlock, FALLING);
  Serial.println("start test");
  Serial.println("IntervalTotal Total Time");

void loop(){
    delay(20);                  // Some delay for "debouncing"
    total++;                    // Update total unlocks
    totalInterval++;            // Update total for interval
    Serial.print(". ");
    Serial.print("# ");
    totalInterval=0;            // Reset the interval count

  1. Bunpei
    February 26, 2012 at 13:27

    I’m sorry that my interest does not exactly focus on this topic. However, it is related to your wonderful Hifiduino code

    Have you ever recognized the problem that “no exact value of unsigned long (4 byte length) DPLL counter value can be read-out without any latching mechanism over 4 registers (register #28 – #31)”?

    Some Japanese Hifiduino users noticed that the lock frequency displayed varies significantly when a “synchronous clocking scheme” is adopted. Chiaki gave me a good explanation on this. Our conclusion is “ES9018 chip lacks an adequate latch and read mechanism for DPLL value or a possible method is not disclosed on its datasheet.”

    The DPLL counter in the chip has a count value representation corresponding to “unsigned long” in Arduino. The maximum value 0xffffffff matches the MCLK frequency. In the case of MCLK 90.3168MHz, DATA_CLK of 2.8224MHz is represented as the value 0x08000000. However, in actual situations, it fluctuates, for example, 0x7FFFFFFF – 0x08000001. While we read out register #28 – #31 values one by one, the whole value changes and each byte changes. In the worst case, an obtained value of DPLLNum shows 0x80FFFFFF or 0x7F000000.

  2. Bunpei
    February 26, 2012 at 13:38

    Sorry. I made terrible mistakes on numbers.

    [incorrect] for example, 0x7FFFFFFF – 0×08000001
    [correct] for example, 0x07FFFFFF – 0×08000001

    [incorrect] 0x80FFFFFF or 0x7F000000
    [correct] 0x08FFFFFF or 0x07000000

    • BlogGeanDo
      February 27, 2012 at 23:53

      Hi Bumpei, you are right, the calculated number can vary widely with a small change in the 32 bit value, if you happen to be right at the “edge” of that number. I did a quick calculation and the frequency will show in the worse case (for an actual frequency of 2.8224Mhz) 3.1752 Mhz or 2.4696 Mhz.

      I have not seen such variation of PCM, but I guess it will only happen if you use the 90.316800 clock

      A side note: I thought in synchronous mode, the dpll is bypassed

  3. Bunpei
    February 28, 2012 at 14:53

    The problem is not 90.3168 MHz specific. Whenever you use any clock frequency of 2**n x fs, you will encounter the problem.

    According to my memory, Russ pointed-out this somewhere before. DPLL can’t be bypassed by any means. He expressed it like this. “DPLL is free-wheeling in synchronous master clocking”.
    On the other hand, OSF can be bypassed and “Jitter eliminating functionality” can be turned off. However, for DSD, we can’t bypass OSF.

    • BlogGeanDo
      February 28, 2012 at 18:53

      Hmmm… I used the formula to determine sample rate, and the value 0x07FFFFFF – 0×08000001 for DPLL corresponds to 44.1KHz (I2S) if the clock is 90.316800 MHz. I have never seen that value move more than 1 Hz.

  4. September 14, 2016 at 14:59

    Blogger Template

  5. September 14, 2016 at 16:10

    kangen water

  6. September 14, 2016 at 16:21

    harrisburg bankruptcy attorney

  7. September 14, 2016 at 16:24

    hyundai hybryd

  8. September 14, 2016 at 18:21

    Super yacht stewardess

  1. March 8, 2012 at 20:01
  2. September 24, 2012 at 13:11

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s