More on Sabre32 I2S Locking
Perusing the old diyaudio threads (circa 2006), I came to a thread describing the initial designs of the Sabre DAC chip. The ASRC was being designed by Dustin Forman and included a SPDIF receiver. The SPDIF receiver was designed to be superior to any current design, being able to lock into an incoming signal even in the presence of large amount of jitter. This post summarizes the capabilities of the receiver:
“…I did however do a side by side test with my ASRC and the CS8421 looses lock with about 50ns of sine jitter added to the SPDIF stream (Tested with APS2) . Then with my ASRC it still maintained lock with up to 400ns (of sine) jitter…”
The output of the SPDIF receiver is connected to the input of the ASRC. In this post, Dustin shared the challenges of designing the ASRC:
“…designing the ASRC I ran into the problem that the higher my “PLL” bandwidth, the worse the SRC got. Lowering the loop bandwidth does create a better SRC, however something bad happens. If the bandwidth is too low, and your source sample rate is not rock solid (jitter, or just any slight frequency variation) then the locked output would get tiny glitches in it when the ASRC accidentally missed an input sample point or grabbed one twice.
Imagine I lock my “PLL” to the input rate at say 44.10000 kHz and then lowered the loop bandwidth so low it could not respond to the input rate changing to 44.10001 kHz before the PLL misses one of the input samples since it is only looking for data at 44.10000 kHz but the data is now actually coming at 44.10001 kHz.
This was the hardest part of the ASRC design: having enough loop bandwidth to handle source data rate variation, but not too much that it causes errors in the SRC.”
The ASRC as a standalone product was never released, but the technology was incorporated in the ESS DAC chip.
From the above information, one can probably deduce that the SPDIF receiver, being an “integral part” of the ASRC, will enable additional jitter suppression as compared to I2S input.
Update Feb, 2012: The current understanding is that with the same setting the DPLL for the I2S input is narrowed 64X, thus the “difficulty” in locking to the signal