Reading Buffalo II SPDIF Sample Rate
I have implemented reading the DPLL register in Buffalo II DAC. Shown in the photo is the sample rate in Hz for a 44.1K SPDIF signal. Previously I had used TPA’s AC-1 prototype to read the sample rate as shown in this post. As expected the results are exactly the same.
In this implementation the sample rate is read/updated once every two seconds, but this is configurable in the code. The new version of the code has been posted here.