Ian’s FIFO reclocker and Buffalo III DAC
Here is a summary of the information regarding the FIFO reclocker (mostly from Ian and mostly from diyaudio). It is getting hard to sift through all the good information.
In particular, I have focused on its application with the Buffalo III DAC which seems a very popular combination.
1- “Normal” connection to Buffalo III DAC
That is in asynchronous mode: Bitclock, LRclock and Data. The master clock signal from the FIFO reclocker is not connected. BIII operates in asynchronous mode generating its own local master clock. This is the default operation of the Buffalo DAC (I, II, III)
(Most photos-which are excellent- are also from Ian)
Buffalo III DPLL setting: default
According to the documentation, the default setting is the same as the “BEST” setting. Best setting works all the time for any input configuration. It is said that with this setting, the DPLL is set “automatically”. I think this is what “automatically” means: the DPLL sets the bandwidth depending on the incoming sample rate. It likely selects wide bandwidth values. It definitely does not attempt to choose the lowest bandwidth possible.
Then I connected the FIFO I2S output into BIII via U.FL coaxial cables…The result was quite impressed. I don’t want to say it’s perfect, but I have to say it’s very close to (perfect). I tried a couple of different kind of XO and found that the sound of ESS9018 still quite sensitive to the jitter from the input digital audio stream. I suspect the internal DPLL still has to trace the input clock to get lock with it. So, the clock jitter, outside the DPLL bandwidth, will still be introduced into DAC, which usually, is the close in phase noise. While the final phase noise within the DPLL bandwidth will be decided by the performance of the internal DPLL (phase noise floor).
No click noise at all with same 192Khz input.
I use BIII default setting so far with all the switch jumpers at off position. I don’t think this optimized for all the sample rates..
Buffalo III DPLL setting: lowest (post 523):
Yes, when I set the switch to “lowest”, I got drop-offs too. It sounds a little bit better for me, but I gave up after half hour ‘warm up’
DPLL setting for 192KHz sample rate material (post 528)
I have to set bandwidth to ‘low-middle’ to achieve long term stable lock with 192Khz I2S
Earlier experiments have shown that the “warm up period” – the time it takes for the local clock in combination with a source clock to stabilize and thus allow the DPLL to operate with no drop-offs in its lowest bandwidth setting- could be up to one hour. It seems that using the FIFO reclocker did not improve this condition. If feeding a signal with jitter approaching a practical zero value still causes drop-offs -even after half an hour, then one may conclude that the lower settings in the Sabre32 DPLL were specified perhaps to push the limits of the design and not so much for “normal operation”.
2- Synchronous connection to Buffalo III DAC
If the source signal is of low enough jitter, then there is no advantage of using the asynchronous reclocker in the Sabre32 DAC to eliminate jitter since there is practically no jitter to be eliminated. The FIFO reclocker is an excellent candidate (at the present, I would even say “the best”) for synchronous connection with the Buffalo/Sabre DAC. In addition, high quality clocks -similar in quality to the clock used in Buffalo DAC- can be used in the FIFO clock board which further eliminates the need of generating a high quality local clock.
Because the Buffalo DAC was not designed for easy switching to synchronous operation, in order to use it in synchronous mode, the local clock needs to be disabled or removed (see post 542)
Then some king of connector is installed. Here, a U.FL socket is installed.
The external clock is delivered though a coax cable.
With this setup, Ian reported the following results:
It runs right away without any hesitating. The LOCK LED keeps lighting all the way indicating it is synchronized with the input I2S stream unconditionally even I set the bandwidth switches to ‘lowest’ and run music at 192KHz from an USB.
In my configuration, ESS9018 sounds great in both of the modes, sync and async. I even couldn’t tell which one is better. But there is slightly difference on the sound style. Async is more like ESS9018 while sync is more like classical high-end DACs. I usually don’t talk much about the sound, because too many psychological factors and personal feelings mixed. I’ll left this part to others, trust your ears and try to find out the best parameter settings of 9018 for the sync mode.
3- Switching between synchronous and asynchronous mode (post 745)
If the source clock is not of the best quality, then it is advantageous to use the local (high quality, low jitter) clock of the Buffalo DAC and leverage the ASRC function to remove jitter. The Buffalo DAC was designed to always work in asynchronous mode and does not have an easy way to switch the local clock in and out of operation.
Ian designed a small carrier board that allows manual switching between synchronous and asynchronous mode. The clock carrier board is connected to the Buffalo III board through a 3-pin header. The Buffalo III DAC was designed with this kind of mod in mind so there are through hole connectors under the clock; the Buffalo II does not have such connectors making the modification a bit more challenging.
For asynchronous mode, manually insert the clock into the socket
For synchronous operation, remove the clock and connect the external clock signal
It would be nice to have some electronic way to switching the clocks (so switching can be automated with an external microprocessor such as Arduino)
What to do with a Buffalo II?
Here is an implementation reported at the TPA forums:
Pin 24 on the ESS chip is the Xtal in pin. As wktk smile said, R17 (RHS of this resistor when the TPA logo is at the top of the board) is connected to the Crystek clock output, which makes a convenient soldering point.
I unpowered the separate supply to the Crystek crystal, then connected up the Hiface clock output to this resistor pad using some Mil coax cable I had lying around. Note I grounded the source end of the coax but not the destination to avoid a ground loop but shield this high frequency signal.
Mental note – pinouts from the dot on the ESS chip go counter clockwise…and the Crystek pinout then would have made sense too…for the Crystek, pin 1 is bottom left, pin 2 bottom right, pin 3 is top right (Clock out)…
Anyhow, it works and initial impressions are positive with the music having excellent drive (PRAT), the bass is very solid, and great inner detail (OK it had lots of the latter before). Well worth trying this guys!
4- Additional enhancements
Further enhancements to the FIFO kit has been implemented through both experience and user feedback.
U.FL signal input connector board for BIII DAC (post 743)
Ian reported the following improvement:
I did some test with this new adapter on my BIII yesterday. It works very well. I’ve noticed some improvement: With BIII (DPLL bandwidth set to lowest) working with I2S FIFO at SYNC mode, If feeding signals with this adapter and U.FL cables, DPLL locks solid never lost; However, without this adapter and U.FL cables, it will lost lock occasionally(every 10 minutes roughly).
Hmmm… this means that the bitclock, even if derived from the same master clock, can experience some disturbances resulting in phase noise with respect to the master clock (the master clock was already connected with a U.FL socket). I think even in asynchronous mode, the use of U.FL would be beneficial.
Multi-frequency clock board (post 837).
After Ian reported good results with the Silicon Labs Si570 clock, I decided to do some research on my own and documented my findings here: link. The advantage of the Si570 programmable clock is that you can generate “any” frequency you need by programming the registers through an I2C connection. This is useful especially since good clocks in frequencies that are “common” to audio equipment are no longer manufactured.
In this post, Ian explains the advantages and disadvantages of a Si570 based clock board:
- Generates low jitter audio clock for multi-frequencies with one chip solution. Especially for some frequencies for which very hard to get good audio clocks.
- Not that sensitive to the power supply.
- To cover the full digital audio frequency range, the cost will be less than using CCHD957 or other low jitter oscillators.
- Supports almost all kinds of applications which need low jitter digital audio clocks such as CD players, SACD players, Network/HD players, DACs, USB interface, ASRCs,DSPs…… (If used as a standalone board)
- Integrates seamlessly with FIFO project to allow switching between different Fs.
- Very flexible and can be calibrated under the software support.
- Close-in phase noise performance is not as good as CCHD957 or sc-cut oscillators.
- Need software driver when switching frequency (not all the time).
- 100mA power consumption which is a bit higher than normal oscillators.
I can think of yet another advantage: Since the frequency can be adjusted in 1 Hz increment, the frequency can be adjusted in order to match the frequency of the incoming data. With this capability, the FIFO fill levels can be adjusted in order to reduce its latency.
Notice the ATMEGA 8 microprocessor which is used to program the Si570 clock which is an I2C device
The first prototype of Si570 based clock board was down. With the single programmable XO, now I got 11.2896, 12.2880, 16.9344, 18.4320, 22.5792, 24.5760, 33.8688, 45.1584, 49.1520, 90.3168, 98.3040 MHz. Switching between frequencies will take only a couple of ms. Pretty amazing for such a small gear. More information here [post 881]
Phase noise comparison with the Crystek 957 device and the Crystek 950:
|Frequency||Si570||CCHD-957 (49.152 MHz)||CCHD-950 (80 MHz)|
||-112 dB||-129 dB||-102 dB
||-122 dB||-153 dB||-135 dB
||-132 dB||-162 dB||-160 dB
||-137 dB||-168 dB||-166 dB
||-144 dB||-168 dB||-166 dB|
Most of the phase noise comes from the close-in frequencies. As can be seen in the table, the Si570 clock cannot match the Crystek 957, but compared to the on-board clock in the Buffalo DAC, and especially compared with the original clock that came with the Buffalo II (the model I currently have), the close-in phase noise values are comparable or even better.
If we calculate the RMS jitter we obtain the following:
(Assume the 10 Hz jitter value for the Si570 can be obtained by extending the graph following the same characteristics slope as that shown by other clocks. We will assume a value of -82 dB)
- For Si570 (assume 90.3168 MHz): 052 psec RMS
- For CCHD-950 -80MHz: 1.90 psec RMS
According to Ian’s impressions (with a evaluation board) [link]
I’m having an original Si570 evaluation board, so I got chance tasting it on my FIFO platform before I really finish the clock board. During the real listening test, the sound of Si570 was quite impressed. It comes with much more details and crystal clear wide and deep 3D imaging. Actually I tested a whole bunch of clocks. Si570 beat all of them except CCHD957. It’s better than what I expected. So, I decided giving the Si570 clock board a try.
According to Ian’s next impression with his finished board [Post 913]
…Another discovery is, ESS9081 sounds different for a same 44.1 KHz stream with different MCLK frequencies, for example 45.1584MHz and 90.3168MHz. Hard to tell which one is better, but the sound style is a bit different indeed. I know it’s the internal up-sampling digital filter, different performance for different MCLK.
Plans for having the clock board be battery powered
Although the Silabs official document mentioned that Si570 is not quite sensitive to the PSU noise, I found it’s not true, at least for this application. The close-in phase noise performance of Si570 is not as good as CCHD950, 957. So, to compete with them, Si570 need better low noise PSU. Both 1/f noise of PSU and the XO crystal itself contribute to the close-in phase noise. After I bypassed the on board low noise LDO and make the Si570 directly powered by a LiFeP04 3.4V battery cell, ESS9018 sounds better with more details and more liquid.
Si570 is a bit special case. It comes with whole DSPLL circuit but a pure XO. I’ll design a battery manager board later on to make the battery as a standard equipped power supply rather than just a testing configuration.
With a programmable clock, you can also experiment with different oversampling and oversampling bypass as documented in this post [link]
There is a V2 of the Si570 Board [post 1512]
- More frequencies
- More connection options
- Support for different regulators
Here is comparing V1 and V2
5- Firmware capabilities
This set-up summary is derived from the documentation available for download at diyaudio. So far there has been two major versions of the firmware: The firmware that came with the devices from the first group-buy and the firmware that came with the devices from the second group-buy.
- First group-buy information and documentation: [link]
- Second group-buy information and documentation: [link]
- The firmware is factory upgradable for free and you only have to pay for shipping [post 724]
|Feature||Original Firmware (v. 3.30)
||Updated Firmware (v. 3.80)||Comments|
|FIFO Input format
||I2S (32bit and 16bit)
||I2S, LJ (32bit and 16bit). RJ (16 bit and 24 bit)||Most “modern” sources are I2S 32bit. Upgraded FW makes it a universal re-clocker. For example, you can connect to the I2S connections of a CD ROM
|Output Master clock (single clock board)
||Fixed 256 Fs
||Fixed 256 Fs and Fixed 512 Fs
||The single clock board does not detect the input sample rate so the XO frequency must match the input sample rate to produce the fixed output master clock FS (Note 1)
|Output Master clock (dual clock board)
||Automatic switching 128Fs, 256Fs, 512Fs and 1024 Fs
||Automatic switching 128Fs, 256Fs, 512Fs and 1024 Fs||Automatic input sample rate detection. (Note 2)
||32bit I2S and 32bit LJ
||LJ to integrate FIFO with some DSPs or DACs which do not accept I2S input, for example, PMD100, SM5842, SM5843|
1- For example, if the input sample frequency is 44.1 KHz, then the user must choose a XO of 11.2896 MHz (44.1×256). This also means that for 44.1KHz, the maximum speed XO that can be used is 22.5792 MHz (with the new firmware). This is the lowest frequency available for the Crystek CCHD-957 clock and was the main reason Ian increased the FS for the single XO board. This board is only suitable if you only have to deal with a single sample rate because changing the input sample rate requires that you manually change the XO and/or set jumpers.
2- The double XO clock board has a frequency management MCU. During normal operation, this MCU will run at deep sleep mode, or power down mode. In this mode, all of the clocks, include CPU clock, IO clock and watchdog clock, are stopped. That means the MCU do not generate any EMI noise at this time. When the frequency detecting logic on the FIFO board finds that the input I2S frequency has changed, it will wake up the MCU by pulling down the interrupt line, and at same time mute the I2S output. After the wake-up, the MCU will set a new MCLK frequency as well as the *Fs according to the information provided by the FIFO board. (Post 54)
Firmware version history (as of August 20, 2012):
- V3.30 For group-buy I
- V3.50 Implements 512Fs default XO support in single clock board
- V3.60 Implements left justified output format
- V3.70 Implements left justified, 16/24bit right justified input format
- V3.75 fixed a bug on switching between 44.1KHz and 48KHz with dual clock board running at dual speed mode
- V3.80 for group-buy II (Post 457)
6- Power Requirements
From the manual
- 6V 500mA DC
- Absolute minimum voltage: 4.5 V
- Absolute maximum voltage 6.7 V
FIFO Board Setup
There are 4 jumpers (The holes labeled TP41, TP42, TP43 and TP48 in the photo) that can be used to select input format, output format and single clock board FS operation. The jumpers are either left open in their factory configuration or can be shorted to ground.
FIFO Input Format
|Jumper TP41||Jumper TP42
||Open||I2S 16bit-32bit (Original firmware only supports this mode)
|Open||Ground||Right Justified 16bit
|Ground||Open||Left Justified 16-bit-32bit
|Ground||Ground||Right Justified 24bit
FIFO Output Format and Single Clock Board Master Clock Operation
||Jumper TP48||Master Clock|
|Ground||Left Justified (32 bit)
TP48 only takes effect if you use the single XO board. If you use the double XO board, this setting is ignored
Single Oscillator Board Setup
You must choose the correct frequency for the oscillator depending on what sample rate you desire:
If your source sample is 44.1KHz, then these are the only two choices for the oscillator frequency
- 11.2896 MHz (must set jumper TP48: open in the FIFO board)
- 22.5792 MHz (must set jumper TP48: ground in the FIFO board) -New FW
If your sample rate is 96KHz, then these are the only two choices:
- 24.576 MHz (must set jumper TP48: open in the FIFO board)
- 49.152 MHz (must set jumper TP48: ground in the FIFO board) -New FW
The board tells you which oscillator to use. With the new firmware, you can use double the speed by setting the jumper to support 512 Fs
Dual Oscillator Board Setup
The dual clock board also has two sets of jumpers that are used to tell the device whether you are using “high speed” or “low speed” oscillators. These jumpers are already installed from the factory as shown in the photo below.
Choosing the oscillators
Choose the oscillators in accordance to input sample rate and required/supported Master clock frequencies as shown in the table below. In addition, one oscillator is to support the 44KHz family of frequencies and the other oscillator is to support the 48KHz family of frequencies. Further, the frequencies of the oscillators can at most be one multiple apart. For example you can use a 45.1584MHz clock and a 24.576Mhz clock, but you cannot use a 11.2896 MHz clock and a 49.152 MHz clock in your dual clock board
|45.1584MHz / 49.152MHz||1024Fs||512Fs||256Fs||128Fs|
|22.5792MHz / 24.576MHz||512Fs||256Fs||128Fs||Not supported
|11.2896 MHz / 12.288MHz||256Fs||128Fs||Not supported||Not supported|
Master clock compatibility
Different DACs support different master clock Fs for the different input sample rates. I’ve summarized the supported master clock Fs for popular DACs. Before choosing the oscillators for the clock board, make sure the master clock Fs is supported by the target DAC.
9- Where is my own FIFO reclocker?
It is still in the box. I can’t believe I’ve had it since March of this year. Life has been taking away time from audio hobby :-). At least I started to review the available information and documentation (which I’ve summarized here, so I won’t forget)
However, based on what Ian has reported, I don’t expect it to behave too much different from my current source with respect to drop-offs. If you see item #1 above, drop-offs are expected with DPLL set to lowest.
Improvements are expected only with synchronous connection, and that would require removing the local oscillator which I am currently hesitant of doing.
In the mean time, I will send it back for firmware upgrade.